📄 keyboard.lis
字号:
00DC .dbline 78
00DC ; UDR = dataLen;
00DC 6CB9 out 0xc,R22
00DE .dbline 79
00DE 4A2D mov R20,R10
00E0 0BC0 xjmp L51
00E2 X0:
00E2 .dbline 79
00E2 ; for( i = startP; i < dataLen + startP; i ++ ){
00E2 L52:
00E2 .dbline 80
00E2 L53:
00E2 .dbline 80
00E2 5D9B sbis 0xb,5
00E4 FECF rjmp L52
00E6 .dbline 81
00E6 80E0 ldi R24,<_tbuf
00E8 90E0 ldi R25,>_tbuf
00EA E42F mov R30,R20
00EC FF27 clr R31
00EE E80F add R30,R24
00F0 F91F adc R31,R25
00F2 2080 ldd R2,z+0
00F4 2CB8 out 0xc,R2
00F6 .dbline 82
00F6 L49:
00F6 .dbline 79
00F6 4395 inc R20
00F8 L51:
00F8 .dbline 79
00F8 262E mov R2,R22
00FA 2A0C add R2,R10
00FC 4215 cp R20,R2
00FE 88F3 brlo L53
0100 .dbline 83
0100 17C0 xjmp L41
0102 X1:
0102 .dbline 83
0102 ; while( !( UCSRA & BIT( UDRE ) ) );
0102 ; UDR = tbuf[i];
0102 ; }
0102 ; } else {
0102 L55:
0102 .dbline 84
0102 L56:
0102 .dbline 84
0102 ; while( !( UCSRA & BIT( UDRE ) ) );
0102 5D9B sbis 0xb,5
0104 FECF rjmp L55
0106 .dbline 85
0106 ; UDR = command;
0106 0CB9 out 0xc,R16
0108 L58:
0108 .dbline 86
0108 L59:
0108 .dbline 86
0108 ; while( !( UCSRA & BIT( UDRE ) ) );
0108 5D9B sbis 0xb,5
010A FECF rjmp L58
010C .dbline 87
010C ; UDR = dataLen;
010C 6CB9 out 0xc,R22
010E .dbline 88
010E 4A2D mov R20,R10
0110 0BC0 xjmp L64
0112 X2:
0112 .dbline 88
0112 ; for( i = startP; i < dataLen + startP; i ++ ){
0112 L65:
0112 .dbline 89
0112 L66:
0112 .dbline 89
0112 5F9B sbis 0xb,7
0114 FECF rjmp L65
0116 .dbline 90
0116 80E0 ldi R24,<_rbuf
0118 90E0 ldi R25,>_rbuf
011A E42F mov R30,R20
011C FF27 clr R31
011E E80F add R30,R24
0120 F91F adc R31,R25
0122 2CB0 in R2,0xc
0124 2082 std z+0,R2
0126 .dbline 91
0126 L62:
0126 .dbline 88
0126 4395 inc R20
0128 L64:
0128 .dbline 88
0128 262E mov R2,R22
012A 2A0C add R2,R10
012C 4215 cp R20,R2
012E 88F3 brlo L66
0130 .dbline 92
0130 ; while( !( UCSRA & BIT( RXC ) ) );
0130 ; rbuf[i] = UDR;
0130 ; }
0130 ; }
0130 L41:
0130 .dbline 93
0130 ; SEI();
0130 7894 sei
0132 .dbline -2
0132 L39:
0132 0E940000 xcall pop_gset3
0136 .dbline 0 ; func end
0136 0895 ret
0138 .dbsym r i 20 c
0138 .dbsym r dataLen 22 c
0138 .dbsym r startP 10 c
0138 .dbsym r buf 18 pc
0138 .dbsym r command 16 c
0138 .dbend
0138 .dbfunc e port_init _port_init fV
.even
0138 _port_init::
0138 .dbline -1
0138 .dbline 97
0138 ; }
0138 ;
0138 ; void port_init(void)
0138 ; {
0138 .dbline 98
0138 ; PORTA = 0x00;
0138 2224 clr R2
013A 2BBA out 0x1b,R2
013C .dbline 99
013C ; DDRA = 0xFF;
013C 8FEF ldi R24,255
013E 8ABB out 0x1a,R24
0140 .dbline 100
0140 ; PORTB = 0xFF;
0140 88BB out 0x18,R24
0142 .dbline 101
0142 ; DDRB = 0xFF;
0142 87BB out 0x17,R24
0144 .dbline 102
0144 ; PORTC = 0xF0; //m103 output only
0144 80EF ldi R24,240
0146 85BB out 0x15,R24
0148 .dbline 103
0148 ; DDRC = 0x0F;
0148 8FE0 ldi R24,15
014A 84BB out 0x14,R24
014C .dbline 104
014C ; PORTD = 0xFF;
014C 8FEF ldi R24,255
014E 82BB out 0x12,R24
0150 .dbline 105
0150 ; DDRD = 0x00;
0150 21BA out 0x11,R2
0152 .dbline -2
0152 L68:
0152 .dbline 0 ; func end
0152 0895 ret
0154 .dbend
0154 .dbfunc e timer0_init _timer0_init fV
.even
0154 _timer0_init::
0154 .dbline -1
0154 .dbline 113
0154 ; }
0154 ;
0154 ; //TIMER0 initialisation - prescale:64
0154 ; // WGM: Normal
0154 ; // desired value: 1mSec
0154 ; // actual value: 1.000mSec (0.0%)
0154 ; void timer0_init(void)
0154 ; {
0154 .dbline 114
0154 ; TCCR0 = 0x00; //stop
0154 2224 clr R2
0156 23BE out 0x33,R2
0158 .dbline 115
0158 ; TCNT0 = 0x83; //set count
0158 83E8 ldi R24,131
015A 82BF out 0x32,R24
015C .dbline 116
015C ; OCR0 = 0x7D; //set compare
015C 8DE7 ldi R24,125
015E 8CBF out 0x3c,R24
0160 .dbline 117
0160 ; TCCR0 = 0x03; //start timer
0160 83E0 ldi R24,3
0162 83BF out 0x33,R24
0164 .dbline -2
0164 L69:
0164 .dbline 0 ; func end
0164 0895 ret
0166 .dbend
.area vector(rom, abs)
.org 36
0024 0C94B300 jmp _timer0_ovf_isr
.area text(rom, con, rel)
0166 .dbfile E:\AVRATM~1\key_board\keyboard.c
0166 .dbfunc e timer0_ovf_isr _timer0_ovf_isr fV
.even
0166 _timer0_ovf_isr::
0166 8A93 st -y,R24
0168 9A93 st -y,R25
016A 8FB7 in R24,0x3f
016C 8A93 st -y,R24
016E .dbline -1
016E .dbline 122
016E ; }
016E ;
016E ; #pragma interrupt_handler timer0_ovf_isr:10
016E ; void timer0_ovf_isr(void)
016E ; {
016E .dbline 123
016E ; TCNT0 = 0x83; //reload counter value
016E 83E8 ldi R24,131
0170 82BF out 0x32,R24
0172 .dbline 124
0172 ; delay_counter ++;
0172 80911E00 lds R24,_delay_counter
0176 90911F00 lds R25,_delay_counter+1
017A 0196 adiw R24,1
017C 90931F00 sts _delay_counter+1,R25
0180 80931E00 sts _delay_counter,R24
0184 .dbline 125
0184 ; key_counter ++;
0184 80911A00 lds R24,_key_counter
0188 90911B00 lds R25,_key_counter+1
018C 0196 adiw R24,1
018E 90931B00 sts _key_counter+1,R25
0192 80931A00 sts _key_counter,R24
0196 .dbline 126
0196 ; scom_counter ++;
0196 80911C00 lds R24,_scom_counter
019A 90911D00 lds R25,_scom_counter+1
019E 0196 adiw R24,1
01A0 90931D00 sts _scom_counter+1,R25
01A4 80931C00 sts _scom_counter,R24
01A8 .dbline -2
01A8 L70:
01A8 8991 ld R24,y+
01AA 8FBF out 0x3f,R24
01AC 9991 ld R25,y+
01AE 8991 ld R24,y+
01B0 .dbline 0 ; func end
01B0 1895 reti
01B2 .dbend
01B2 .dbfunc e uart0_init _uart0_init fV
.even
01B2 _uart0_init::
01B2 .dbline -1
01B2 .dbline 135
01B2 ; }
01B2 ;
01B2 ; //UART0 initialisation
01B2 ; // desired baud rate: 9600
01B2 ; // actual: baud rate:9615 (0.2%)
01B2 ; // char size: 8 bit
01B2 ; // parity: Disabled
01B2 ; void uart0_init(void)
01B2 ; {
01B2 .dbline 136
01B2 ; UCSRB = 0x00; //disable while setting baud rate
01B2 2224 clr R2
01B4 2AB8 out 0xa,R2
01B6 .dbline 137
01B6 ; UCSRA = 0x00;
01B6 2BB8 out 0xb,R2
01B8 .dbline 138
01B8 ; UCSRC = 0x86;
01B8 86E8 ldi R24,134
01BA 80BD out 0x20,R24
01BC .dbline 139
01BC ; UBRRL = 0x00; //set baud rate lo
01BC 29B8 out 0x9,R2
01BE .dbline 140
01BE ; UBRRH = 0x00; //set baud rate hi
01BE 20BC out 0x20,R2
01C0 .dbline 141
01C0 ; UCSRB = 0x98;
01C0 88E9 ldi R24,152
01C2 8AB9 out 0xa,R24
01C4 .dbline -2
01C4 L71:
01C4 .dbline 0 ; func end
01C4 0895 ret
01C6 .dbend
01C6 .dbfunc e watchdog_init _watchdog_init fV
.even
01C6 _watchdog_init::
01C6 .dbline -1
01C6 .dbline 147
01C6 ; }
01C6 ;
01C6 ; //Watchdog initialisation
01C6 ; // prescale: 32K cycles
01C6 ; void watchdog_init(void)
01C6 ; {
01C6 .dbline 148
01C6 ; WDR(); //this prevents a timout on enabling
01C6 A895 wdr
01C8 .dbline 149
01C8 ; WDTCR = 0x0A; //WATCHDOG ENABLED - dont forget to issue WDRs
01C8 8AE0 ldi R24,10
01CA 81BD out 0x21,R24
01CC .dbline -2
01CC L72:
01CC .dbline 0 ; func end
01CC 0895 ret
01CE .dbend
01CE .dbfunc e init_devices _init_devices fV
.even
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