util.h

来自「ESS3890+SL原代码（1*16内存）」· C头文件 代码 · 共 386 行

/* Copyright 1996-2003, ESS Technology, Inc.				*/
/* SCCSID @(#)util.h	4.16 12/14/04 */

/*
 * $Log$
 */

#ifndef __UTIL_H__
#define __UTIL_H__

#include "mvd.h"
#include "common.h"

register volatile int *mvd asm("r27");

#define lwpeek(addr)		mvd[addr]
#define	lwpoke(addr, data)	mvd[addr] = data

#ifdef MPEG1

#ifdef BIG_MEM
#define DMAWIDTH0       128	/* 0x080 for refresh */
#define BIG_MEM_BIT	0x20	/* bit 5 of BUSCON_DMA_SCALE_TYPE for ES3986 */
#else
#define DMAWIDTH0       256	/* 0x100 for refresh */
#define BIG_MEM_BIT	0x0	/* not used */
#endif

/* for Y, we will use INC2_Y */
#define DMAWIDTH2_E2_UV    (DISP_info[E2].wUV)
#define DMAWIDTH1_E2_Y    ((704*3/4)/4)
#define DMAWIDTH1       (176/4)	/* I/P screen */
#define DMAWIDTH2       ((176*3/4) /4)	/* B screen */
#else /*MPEG1*/
#define DMAWIDTH0       256	/* 0x100 for refresh */
#define DMAWIDTH1       (360/4)	/* uv screen */
#define DMAWIDTH2       (720/4)	/* y screen */
#endif /*MPEG1*/

/*
 * **************** Risc Interface ****************
 */
#define RIFACE_STLD_IRQSUPRESS	0x0000C000
#define RIFACE_LD_IRQSUPRESS	0x00004000
#define RIFACE_ST_IRQSUPRESS	0x00008000

#define xport_irq		0x00000001
#define tim1_irq		0x00000002
#define tim2_irq		0x00000004
#define vin_irq			0x00000008
#define vout_irq		0x00000010
#define rdma_irq		0x00000020
#define vpcmdq_irq		0x00000040
#define buscon_irq		0x00000080
#define huff_irq		0x00000100
#define host_irq		0x00000200
#define aud_irq			0x00000400
#define tdm_irq			0x00000800
#define gateway_irq		0x00001000
#define debug_irq		0x00002000
	
#define enable_int(ch) {					\
	int tmp;						\
	mvd[riface_irqsuppress] =0;	asm("nop"); asm("nop");	\
	tmp = mvd[riface_irqmask];				\
	tmp |= cat2(ch,_irq);					\
	mvd[riface_irqmask] = tmp;				\
}

#define disable_int(ch) {					\
	int tmp;						\
	mvd[riface_irqsuppress] =0;	asm("nop"); asm("nop");	\
	tmp = mvd[riface_irqmask] ;				\
	tmp &= ~cat2(ch,_irq);					\
	mvd[riface_irqmask] =tmp;				\
}

/*
 * **************** Risc DMA ****************
 */

GBLDEF0(int RDMADoneMask);

#define rdma_transr_enable	0x00000001
#define rdma_tdmw_enable	0x00000002
#define rdma_gater_enable	0x00000004
#define rdma_gatew_enable	0x00000008
#define rdma_hostr_enable	0x00000010
#define rdma_hostw_enable	0x00000020

#define disable_rdma(ch)	lwpoke(rdma_disable,cat3(rdma_,ch,_enable))
#define enable_rdma(ch)		lwpoke(rdma_enable, cat3(rdma_,ch,_enable))
#define clear_rdma_done(ch)	lwpoke(rdma_done, cat3(rdma_,ch,_enable))

#define rdma_xfer(ch, adr, cnt, pri) do {	\
  mvd[rdma_disable] = cat3(rdma_,ch,_enable);	\
  mvd[cat3(rdma_,ch,_addr)] = (int)(adr) >> 1;	\
  mvd[cat3(rdma_,ch,_cnt)] = cnt;		\
  mvd[cat3(rdma_,ch,_pri)] = pri;		\
  mvd[rdma_enable] = cat3(rdma_,ch,_enable);	\
} while (0)

#define	rdma_is_done(ch) \
  (mvd[rdma_done] & cat3(rdma_,ch,_enable))

#define rdma_wait(ch) do {			\
  (void) mvd[rdma_done]; /* read twice */	\
  do {} while (!rdma_is_done(ch));		\
} while(0)


/*
 * **************** Bus Controller DMA ****************
 */
#define buscon_vp_runbit        0x00000001
#define buscon_yscnnr_runbit    0x00000002
#define buscon_yscn_runbit      0x00000004
#define buscon_uscn_runbit      0x00000008
#define buscon_vscn_runbit      0x00000010
#define buscon_ycamnr_runbit    0x00000020
#define buscon_ycam_runbit      0x00000040
#define buscon_ucam_runbit      0x00000080
#define buscon_vcam_runbit      0x00000100
#define buscon_xportv_runbit    0x00000200
#define buscon_xporta_runbit    0x00000400
#define buscon_audioin_runbit	0x00000800
#define buscon_audioout_runbit	0x00001000
#define buscon_hostout_runbit	0x00002000
#define buscon_ref_runbit	0x00004000
#define buscon_b2r_runbit	0x00008000
#define buscon_hufdecv_runbit	0x00010000
#define buscon_hufdeca_runbit	0x00020000
#define buscon_m2h_runbit	0x00040000
#define buscon_hufenc_runbit	0x00080000
#define buscon_h2m_runbit	0x00100000
#define buscon_r2b_runbit	0x00200000

#define buscon_xa1_runbit	buscon_hufenc_runbit
#define buscon_xa2_runbit	buscon_audioin_runbit

#define buscon_dma_deltas_xa1	buscon_dma_deltas_hufenc
#define buscon_dma_xpos_xa1	buscon_dma_xpos_hufenc
#define buscon_dma_ypos_xa1	buscon_dma_ypos_hufenc

#define buscon_dma_deltas_xa2	buscon_dma_deltas_audio_in
#define buscon_dma_xpos_xa2	buscon_dma_xpos_audio_in
#define buscon_dma_ypos_xa2	buscon_dma_ypos_audio_in

#define buscon_a2d_runbit	buscon_audioin_runbit
#define buscon_dma_deltas_a2d	buscon_dma_deltas_audio_in
#define buscon_dma_xpos_a2d	buscon_dma_xpos_audio_in
#define buscon_dma_ypos_a2d	buscon_dma_ypos_audio_in

#define buscon_d2a_runbit	buscon_audioout_runbit
#define buscon_dma_deltas_d2a	buscon_dma_deltas_audio_out
#define buscon_dma_xpos_d2a	buscon_dma_xpos_audio_out
#define buscon_dma_ypos_d2a	buscon_dma_ypos_audio_out

#define BDMA_INC2      0x1000  /* Increment Y position by 2 when DMAing*/
#define BDMA_WIDTH0    0x0000  /* Use width0 for y increments           */
#define BDMA_WIDTH1    0x0200  /* Use width1 for y increments           */
#define BDMA_WIDTH2    0x0400  /* Use width2 for y increments           */
#define BDMA_WIDTH3    0x0600  /* Use width3 for y increments           */
#define BDMA_USEDX     0x0800  /* Use dx for y increments               */
#ifdef JPEG_DEC
#define JPEG_BDMA_WIDTH	BDMA_WIDTH3	/* For JPEG_DEC Use width3 */ 
#endif

#define flush_xportv    0x80
#define flush_xporta    0x40
#define flush_hufenc    0x20
#define flush_r2b       0x10
#define flush_b2r       0x00    /* Doesn't really exists */
#define flush_d2a       0x00    /* Doesn't really exists */

#define DY_MAX	0x80	/* for VCP 0x40 */

#define buscon_is_running(ch) \
  (mvd[buscon_dma_status] & cat3(buscon_,ch,_runbit))

#define buscon_wait(ch) do {		\
  while (buscon_is_running(ch));	\
  gbl_gate_control &= ~flush_##ch;	\
  mvd[gate_control] = gbl_gate_control;	\
} while (0)

#define buscon_wait_timeout(ch, timeout) do {           \
  int timeout_count = 0;                                \
  while (buscon_is_running(ch)) {                       \
    timeout_count++;                                    \
    if (timeout_count > timeout) {                      \
      EPRINTF(("pending_status = 0x%x at %d, %s\n",     \
        mvd[buscon_dma_pending],__LINE__,__FILE__));    \
      break;                                            \
    }                                                   \
  }                                                     \
  gbl_gate_control &= ~flush_##ch;			\
  mvd[gate_control] = gbl_gate_control;			\
} while(0)

#define buscon_disable(ch) mvd[buscon_dma_disable] = cat3(buscon_,ch,_runbit)
#define buscon_enable(ch)  mvd[buscon_dma_enable] = cat3(buscon_,ch,_runbit)

GBLDEF0(int gbl_buscon_irqmasks);

#ifdef BUSCON_IRQ_USE_MACRO 

#define buscon_irq_enable(ch_runbit) do {		\
  do {} while (!(mvd[buscon_dma_status] & ch_runbit));	\
  mvd[riface_irqsuppress] = 0; asm("nop"); asm("nop");	\
  gbl_buscon_irqmasks |= ch_runbit;			\
  mvd[buscon_dma_irqmasks] = gbl_buscon_irqmasks;	\
} while (0)

#define buscon_irq_disable(ch_runbit) do {		\
  mvd[riface_irqsuppress] = 0; asm("nop"); asm("nop");	\
  gbl_buscon_irqmasks &= ~ch_runbit;			\
  mvd[buscon_dma_irqmasks] = gbl_buscon_irqmasks;	\
} while (0)

#endif


#define buscon_zap(ch) do {			\
  buscon_irq_disable(cat3(buscon_,ch,_runbit));	\
  buscon_disable(ch);				\
  /*do {;} while (buscon_is_running(ch));*/	\
} while (0)

#define a2x(a)	((a) & 0x1ff)
#define a2y(a)	((a) >> 9)

#define buscon_xfer(ch, mode, addr, dx, dy) do {			   \
  mvd[cat2(buscon_dma_deltas_,ch)] = ((0x80 - (dy)) << 9) | (0x200 - (dx));\
  mvd[cat2(buscon_dma_xpos_,ch)] = (mode) | a2x(addr);			   \
  mvd[cat2(buscon_dma_ypos_,ch)] = a2y(addr);				   \
} while(0)

#define buscon_quick_BF(ch, addr, mode, BframeComp) do {    \
  mvd[cat2(buscon_dma_xpos_,ch)] = (mode) | a2x(addr);	    \
  mvd[cat2(buscon_dma_ypos_,ch)] = BframeComp + a2y(addr);  \
} while(0)

#define buscon_quick(ch, addr, mode) buscon_quick_BF(ch, addr, mode, 0)


/*
 * **************** RISC fifo ****************
 */
#define GATE_TREMASK    0x02
#define GATE_DWMASK     0x01

#if 1
#define get_riscfifo(answer)	do {				\
    while (!(lwpeek(gate_status) & GATE_DWMASK));		\
    answer = lwpeek(gate_risc_fifo);				\
} while (0)

#define put_riscfifo(data)	do {				\
    while (!(lwpeek(gate_status) & GATE_TREMASK));		\
    lwpoke(gate_risc_fifo,data);				\
} while (0)
#else
#define get_riscfifo(answer)	do {				\
    int timeout = 0;						\
    while (!(lwpeek(gate_status) & GATE_DWMASK)){		\
	timeout++;						\
	if (timeout>0x400000) {					\
	    EPRINTF(("GateRiscFF DW timeout\n")); break;	\
	}							\
    }								\
    answer = lwpeek(gate_risc_fifo);				\
} while (0)

#define put_riscfifo(data)	do {				\
    int timeout = 0;						\
    while (!(lwpeek(gate_status) & GATE_TREMASK)){		\
	timeout++;						\
	if (timeout>0x400000) {					\
	    EPRINTF(("GateRiscFF TRE timeout\n")); break;	\
	}							\
    }								\
    lwpoke(gate_risc_fifo,data);				\
} while (0)
#endif


/* typedefs */
typedef struct {
    int	audio_task;
    int	audio_go;
    int dst_space;
    int	dst_thresh;
    int	src_thresh;
    int	go_limit;
    int	end_limit;
    int	abv_fullness;
    int	as_abv_fullness;
} SCHED_LIMITS;

typedef struct {
    unsigned int psd_offset	:16; /* PSD offset or MP3_framesize */
    unsigned int trk_or_item	:16; /* 0: invalid resume info */

    unsigned int reserved_31	:1;  
    unsigned int state		:4;  
    unsigned int pbc_on		:1;  /* PBC on/off */
    unsigned int height		:1;  /* 0: 288/576, 1: 240/480 */
    unsigned int hi_res		:1;  /* 0: 352x240/288, 1: 704x480/576 */
    unsigned int mmssff		:24; /* absolute (BCD) */
} RESUME_INFO;


/* global variables */
extern	unsigned int *RISC_ptr_realtime, *RISC_cache_realtime;
extern	RESUME_INFO *VCD_ptr_resume_info;

GBLDEF0(int timer2_period);	/* Period for timer2. Set at run time	*/
GBLDEF0(volatile uint timer2_cnt);	/* timer2_cnt */

void	RISC_timer2_interrupt_service(void);
void	RISC_start_timer2(void);
void	RISC_to_dram(int dst, int *srcp, int n);
void    RISC_flush(int start, int n);
void	update_glbTimer(void);
void	risc_fifo_read(int *p, int n);
void	risc_fifo_write(int *p, int n);
void	sram_to_dram(int dst, int *srcp, int n);
void	dram_to_sram(int *dstp, int src, int n);
void	UTIL_flushcache(register unsigned int, unsigned int);
uint	UTIL_hex2bcd(int);
int	UTIL_set_timer2_end(int, uint *);
int	UTIL_reached_timer2_end(int, uint);
int	UTIL_debounce(PFUI, int);
uchar	*hex2string(char *str, int number);
void	swap_values(int *, int *);
void	AS_set_sched_limits(SCHED_LIMITS *);
void	AS_audio_decode_monitor(SCHED_LIMITS *, int);
void	AS_update_abv_gd2wr(SCHED_LIMITS *);
int	AS_audio_encode_monitor(SCHED_LIMITS *);
int	AS_xport_data_end(void);
#if defined(VCDLC) && defined(MY_DEBUG)
void    DBG_my_allocate_trace_buffer(void);
void    DBG_my_log(int, int, int, int);
#else
#define DBG_my_log(type, a0, a1, a2)
#define DBG_my_allocate_trace_buffer()
#endif


#if defined(COMPRESS_MKTBL_DATA) || \
    defined(XSEG1_ON_FLY) || defined(XSEG2_ON_FLY) || \
    defined(XSEG3_ON_FLY) || defined(XSEG4_ON_FLY) || \
    defined(XSEG5_ON_FLY)

#define XSEG1_DATA	0x0001 
#define XSEG1_CODE	0x0002 
#define XSEG2_DATA	0x0004
#define XSEG2_CODE	0x0008
#define XSEG3_DATA	0x0010
#define XSEG3_CODE	0x0020
#define XSEG4_DATA	0x0040
#define XSEG4_CODE	0x0080
#define XSEG5_DATA	0x0100
#define XSEG5_CODE	0x0200
#define XSEG_DATA	(XSEG1_DATA|XSEG2_DATA|XSEG3_DATA\
			|XSEG4_DATA|XSEG5_DATA)
#define XSEG_CODE	(XSEG1_CODE|XSEG2_CODE|XSEG3_CODE\
			|XSEG4_CODE|XSEG5_CODE)
extern int xtra_s1_compress_data_start;
extern int xtra_s1_compress_text_start;
extern int xtra_s2_compress_data_start;
extern int xtra_s2_compress_text_start;
extern int xtra_s3_compress_data_start;
extern int xtra_s3_compress_text_start;
extern int xtra_s4_compress_data_start;
extern int xtra_s4_compress_text_start;
extern int xtra_s5_compress_data_start;
extern int xtra_s5_compress_text_start;

extern void Decompress(int, int, int);
#endif /* XSEG1_ON_FLY || XSEG2_ON_FLY || ... XSEG5_ON_FLY */

#endif /* __UTIL_H__ */