ioport.h
来自「ESS3890+SL原代码（1*16内存）」· C头文件 代码 · 共 433 行 · 第 1/2 页
H
433 行
/* Copyright 1996, ESS Technology, Inc. *//* SCCSID @(#)ioport.h 4.3 08/09/04 *//* * $Log$ */#ifndef __IOPORT_H__#define __IOPORT_H__#include "mvd.h"/* AUX0,AUX1 are open-collector with pull-ups..default at reset is HIGH */GBLDEF(unsigned int shadow_riface_aux1, 0x3); GBLDEF_0(unsigned int shadow_riface_aux2, 0);/* * Since riface_aux1 and riface_aux2 connect to pads, and read/write * to these ports get different values, we should NEVER directly write * to these two registers. Instead, we should have two shadow variables * to keep track of their current values. * * NOTE: For ES3890, AUX2 and AUX4 can only except inputs. Additionally, * AUX2 is internally used to drive the DSC toggle. * */#define LOCK6 mvd[riface_irqsuppress] = (15 - 6)#define LOCK9 mvd[riface_irqsuppress] = (15 - 9)#define SET_AUX0 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 1)#define SET_AUX1 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 2)#if (defined IO3890 || defined IO3898)#define SET_AUX2 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 0x04)#ifdef IO3898#define SET_AUX4 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x11)#else#define SET_AUX4 /* input only */#endif#else#define SET_AUX2 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 0x14)#define SET_AUX4 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x11)#endif /* IO3890 */#define SET_AUX3 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 0x28)#if (defined IO3890 || defined IO3898)#define SET_AUX5 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x22)#define SET_AUX6 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x44)#else#define SET_AUX5 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x44)#define SET_AUX6 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x22)#endif /* IO3890 */#define SET_AUX7 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x88)#define TRISTATE_AUX0 SET_AUX0#define TRISTATE_AUX1 SET_AUX1#define TRISTATE_AUX2 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~0x10)#define TRISTATE_AUX3 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~0x20)#define TRISTATE_AUX4 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x10)#if (defined IO3890 || defined IO3898)#define TRISTATE_AUX5 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x20)#define TRISTATE_AUX6 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x40)#else#define TRISTATE_AUX5 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x40)#define TRISTATE_AUX6 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x20)#endif /* IO3890 */#define TRISTATE_AUX7 LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x80)#define CLEAR_AUX0 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~1)#define CLEAR_AUX1 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~2)#if (defined IO3890 || defined IO3898)#define CLEAR_AUX2 LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~4)#define CLEAR_AUX4 /* input only */#else#define CLEAR_AUX2 LOCK9; shadow_riface_aux1&= ~4; \ mvd[riface_aux1] = (shadow_riface_aux1 |= 0x10)#define CLEAR_AUX4 LOCK9; shadow_riface_aux2 &= ~1; \ mvd[riface_aux2] = (shadow_riface_aux2|= 0x10)#endif /* IO3890 */#define CLEAR_AUX3 LOCK9; shadow_riface_aux1 &= ~8; \ mvd[riface_aux1] = (shadow_riface_aux1 |= 0x20)#if (defined IO3890 || defined IO3898)#define CLEAR_AUX5 LOCK9; shadow_riface_aux2 &= ~2; \ mvd[riface_aux2] = (shadow_riface_aux2|= 0x20)#define CLEAR_AUX6 LOCK9; shadow_riface_aux2 &= ~4; \ mvd[riface_aux2] = (shadow_riface_aux2|= 0x40)#else#define CLEAR_AUX5 LOCK9; shadow_riface_aux2 &= ~4; \ mvd[riface_aux2] = (shadow_riface_aux2|= 0x40)#define CLEAR_AUX6 LOCK9; shadow_riface_aux2 &= ~2; \ mvd[riface_aux2] = (shadow_riface_aux2|= 0x20)#endif /* IO3890*/#define CLEAR_AUX7 LOCK9; shadow_riface_aux2 &= ~8; \ mvd[riface_aux2] = (shadow_riface_aux2|= 0x80)/* * 3208/3210 has built in XOR. One of the inputs to the XOR gate is the * output data of AUX4 (regardless of the state of the tri-state control). * Therefore, writing a 1 to the data is equivalent to setting the input * 1. * * When we change this input, most likely we also want to disable the * tri-state so the signal does not go off chip. */#define SET_IRXOR LOCK9; shadow_riface_aux2 &= ~0x10; \ mvd[riface_aux2] = (shadow_riface_aux2 |= 0x01)#define CLEAR_IRXOR LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x11)#define IS_IRXOR_HIGH ((shadow_riface_aux2 & 0x1) ? 1 : 0)#define AUX0_HIGH (mvd[riface_aux1] & 0x1)#define AUX1_HIGH (mvd[riface_aux1] & 0x2)#define AUX2_HIGH (mvd[riface_aux1] & 0x4)#define AUX3_HIGH (mvd[riface_aux1] & 0x8)#define AUX4_HIGH (mvd[riface_aux2] & 0x1)#if (defined IO3890 || defined IO3898)#define AUX5_HIGH (mvd[riface_aux2] & 0x2)#define AUX6_HIGH (mvd[riface_aux2] & 0x4)#else#define AUX5_HIGH (mvd[riface_aux2] & 0x4)#define AUX6_HIGH (mvd[riface_aux2] & 0x2)#endif /* IO3890 */#define AUX7_HIGH (mvd[riface_aux2] & 0x8)#define AUX0_LOW (!AUX0_HIGH)#define AUX1_LOW (!AUX1_HIGH)#define AUX2_LOW (!AUX2_HIGH)#define AUX3_LOW (!AUX3_HIGH)#define AUX4_LOW (!AUX4_HIGH)#define AUX5_LOW (!AUX5_HIGH)#define AUX6_LOW (!AUX6_HIGH)#define AUX7_LOW (!AUX7_HIGH)#ifdef DSC/* EAUX pins definitions */#include "dsc.h"/* * Following routines are needed with or without 3207/9 */extern void DSC_dead(int); /* Reset the system */#endif#if (defined IO3898 && defined DVE)GBLDEF0(unsigned int shadow_riface_eaux1);GBLDEF0(unsigned int shadow_riface_eaux2);GBLDEF0(unsigned int shadow_riface_eaux3);#define ENABLE_EAUX1(x) LOCK6; mvd[riface_eaux12en] |= (0x0001 << x);#define ENABLE_EAUX2(x) LOCK6; mvd[riface_eaux12en] |= (0x0100 << x);#define ENABLE_EAUX3(x) LOCK6; mvd[riface_eaux34en] |= (0x0001 << x);#define DISABLE_EAUX1(x) LOCK6; mvd[riface_eaux12en] &= ~(0x0001 << x);#define DISABLE_EAUX2(x) LOCK6; mvd[riface_eaux12en] &= ~(0x0100 << x);#define DISABLE_EAUX3(x) LOCK6; mvd[riface_eaux34en] &= ~(0x0001 << x);#define SET_EAUX1_0 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x0101)#define SET_EAUX1_1 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x0202)#define SET_EAUX1_2 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x0404)#define SET_EAUX1_3 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x0808)#define SET_EAUX1_4 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x1010)#define SET_EAUX1_5 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x2020)#define SET_EAUX1_6 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x4040)#define SET_EAUX1_7 LOCK6; \ mvd[riface_eaux1_dc] = (shadow_riface_eaux1 |= 0x8080)#define SET_EAUX2_0 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x0101)#define SET_EAUX2_1 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x0202)#define SET_EAUX2_2 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x0404)#define SET_EAUX2_3 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x0808)#define SET_EAUX2_4 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x1010)#define SET_EAUX2_5 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x2020)#define SET_EAUX2_6 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x4040)#define SET_EAUX2_7 LOCK6; \ mvd[riface_eaux2_dc] = (shadow_riface_eaux2 |= 0x8080)#define SET_EAUX3_0 LOCK6; \ mvd[riface_eaux3_dc] = (shadow_riface_eaux3 |= 0x0101)#define SET_EAUX3_1 LOCK6; \ mvd[riface_eaux3_dc] = (shadow_riface_eaux3 |= 0x0202)#define SET_EAUX3_2 LOCK6; \ mvd[riface_eaux3_dc] = (shadow_riface_eaux3 |= 0x0404)#define SET_EAUX0 SET_EAUX1_0#define SET_EAUX1 SET_EAUX1_1#define SET_EAUX2 SET_EAUX1_2#define SET_EAUX3 SET_EAUX1_3#define SET_EAUX4 SET_EAUX1_4#define SET_EAUX5 SET_EAUX1_5#define SET_EAUX6 SET_EAUX1_6#define SET_EAUX7 SET_EAUX1_7#define SET_EAUX8 SET_EAUX2_0#define SET_EAUX9 SET_EAUX2_1#define SET_EAUX10 SET_EAUX2_2#define SET_EAUX11 SET_EAUX2_3#define SET_EAUX12 SET_EAUX2_4#define SET_EAUX13 SET_EAUX2_5#define SET_EAUX14 SET_EAUX2_6#define SET_EAUX15 SET_EAUX2_7#define SET_EAUX16 SET_EAUX3_0#define SET_EAUX17 SET_EAUX3_1⌨️ 快捷键说明
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