ad73311cfg_c.c

文件系统在DSP5509上的实现

/*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT ad73311.cdb */

/*  Include Header File  */
#include "ad73311cfg.h"


#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")
#include <csl_chiphal.h>

#include <_csl_gpiohal.h>
#include <_csl_pgpiohal.h>


/*  Config Structures */
EMIF_Config emifCfg0 = {
    0x00a0,        /*  Global Control Register   */
    0xffff,        /*  Global Reset Register   */
    0x2fff,        /*  CE0 Space Control Register 1   */
    0x5fff,        /*  CE0 Space Control Register 2   */
    0x0000,        /*  CE0 Space Control Register 3   */
    0x2fff,        /*  CE1 Space Control Register 1   */
    0x5fff,        /*  CE1 Space Control Register 2   */
    0x0000,        /*  CE1 Space Control Register 3   */
    0x1fff,        /*  CE2 Space Control Register 1   */
    0x5fff,        /*  CE2 Space Control Register 2   */
    0x0000,        /*  CE2 Space Control Register 3   */
    0x1fff,        /*  CE3 Space Control Register 1   */
    0x5fff,        /*  CE3 Space Control Register 2   */
    0x0000,        /*  CE3 Space Control Register 3   */
    0xf948,        /*  SDRAM Control Register 1   */
    0x0080,        /*  SDRAM Period Register   */
    0x0fff,        /*  SDRAM Initialization Register   */
    0x03ff         /*  SDRAM Control Register 2   */
};

MCBSP_Config mcbspCfg0 = {
    0x0000,        /*  Serial Port Control Register 1   */
    0x0000,        /*  Serial Port Control Register 2   */
    0x0040,        /*  Receive Control Register 1   */
    0x0000,        /*  Receive Control Register 2   */
    0x0040,        /*  Transmit Control Register 1   */
    0x0000,        /*  Transmit Control Register 2   */
    0x0000,        /*  Sample Rate Generator Register 1   */
    0x2000,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x000d,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

PLL_Config pllCfg0 = {
    0x0000,        /*  PLL Response After Idle (IAI)   */
    0x0000,        /*  Response to Loss of PLL Core Lock (IOB)   */
    0x0007,        /*  PLL Multiply Value (PLL_MULT)   */
    0x0000         /*  PLL Divide Value (PLL_DIV)   */
};

RTC_Config rtcCfg0 = {
    0x40,        /*  Seconds Register (RTCSEC)   */
    0x00,        /*  Seconds Alarm Register (RTCSECA)   */
    0x23,        /*  Minutes Register (RTCMIN)   */
    0x46,        /*  Minutes Alarm Register (RTCMINA)   */
    0x16,        /*  Hour Register (RTCHOUR)   */
    0x16,        /*  Hour Alarm Register (RTCHOURA)   */
    0x4c,        /*  Day of the Week Register (RTCDAYW)   */
    0x05,        /*  Day of the Month Register (RTCDAYM)   */
    0x03,        /*  Month Register (RTCMONTH)   */
    0x08,        /*  Year Register (RTCYEAR)   */
    0x04,        /*  Periodic Interrupt Selection Register (RTCPINTR)   */
    0x02         /*  Interrupt Enable Register (RTCINTEN)   */
};

WDTIM_Config wdtimCfg0 = {
    0x1000,        /*  WD Timer Period Register (WDPRD)  */
    0x0000,        /*  WD Timer Control Register (WDTCR)  */
    0x1000         /*  WD Timer Secondary Control Register (WDTCR2)   */
};

/*  Handles  */
DMA_Handle hDma0;
MCBSP_Handle hMcbsp0;
MCBSP_Handle hMcbsp1;

/*
 *  ======== CSL_cfgInit() ========  
 */
void CSL_cfgInit()
{
    
    CHIP_RSET(XBSR, 0);
    hDma0 = DMA_open(DMA_CHA0, DMA_OPEN_RESET);
    hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
    hMcbsp1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
        
    EMIF_config(&emifCfg0);
    MCBSP_config(hMcbsp0, &mcbspCfg0);
    MCBSP_config(hMcbsp1, &mcbspCfg0);
    PLL_config(&pllCfg0);
    RTC_config(&rtcCfg0);

    /* You must use DMA_start() in your main code to start the DMA. */

	EMIF_RSET(EMIRST,0xFFFFu);
    GPIO_RSET(IODIR, 0xf);
    GPIO_RSET(IODATA, 0xf);

    GPIO_RSET(AGPIOEN, 0x0);
    GPIO_RSET(AGPIODIR, 0x0);
    GPIO_RSET(AGPIODATA, 0x0);

    GPIO_RSET(GPIOEN, 0x0);
    GPIO_RSET(GPIODIR, 0x0);
    GPIO_RSET(GPIODATA, 0x0);
    
    /* You must use MCBSP_start() in your main code to start the MCBSP. */

    
    /* You must use RTC_start() in your main code to start the RTC. */

    
    /* You must use WDTIM_start() in your main code to start the WDTIM. */

}