at91sam7x256_inc.h

at91sam7x256的AIC已经编译好

#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) ;// (SSC) Detection of any level change on RF input
#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) ;// (SSC) Detection of any edge on RF input
#define 	AT91C_SSC_START_0                    (0x8 <<  8) ;// (SSC) Compare 0
#define AT91C_SSC_STOP            (0x1 << 12) ;// (SSC) Receive Stop Selection
#define AT91C_SSC_STTDLY          (0xFF << 16) ;// (SSC) Receive/Transmit Start Delay
#define AT91C_SSC_PERIOD          (0xFF << 24) ;// (SSC) Receive/Transmit Period Divider Selection
;// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
#define AT91C_SSC_DATLEN          (0x1F <<  0) ;// (SSC) Data Length
#define AT91C_SSC_LOOP            (0x1 <<  5) ;// (SSC) Loop Mode
#define AT91C_SSC_MSBF            (0x1 <<  7) ;// (SSC) Most Significant Bit First
#define AT91C_SSC_DATNB           (0xF <<  8) ;// (SSC) Data Number per Frame
#define AT91C_SSC_FSLEN           (0xF << 16) ;// (SSC) Receive/Transmit Frame Sync length
#define AT91C_SSC_FSOS            (0x7 << 20) ;// (SSC) Receive/Transmit Frame Sync Output Selection
#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) ;// (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) ;// (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) ;// (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) ;// (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) ;// (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) ;// (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
#define AT91C_SSC_FSEDGE          (0x1 << 24) ;// (SSC) Frame Sync Edge Detection
;// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
;// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
#define AT91C_SSC_DATDEF          (0x1 <<  5) ;// (SSC) Data Default Value
#define AT91C_SSC_FSDEN           (0x1 << 23) ;// (SSC) Frame Sync Data Enable
;// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
#define AT91C_SSC_TXRDY           (0x1 <<  0) ;// (SSC) Transmit Ready
#define AT91C_SSC_TXEMPTY         (0x1 <<  1) ;// (SSC) Transmit Empty
#define AT91C_SSC_ENDTX           (0x1 <<  2) ;// (SSC) End Of Transmission
#define AT91C_SSC_TXBUFE          (0x1 <<  3) ;// (SSC) Transmit Buffer Empty
#define AT91C_SSC_RXRDY           (0x1 <<  4) ;// (SSC) Receive Ready
#define AT91C_SSC_OVRUN           (0x1 <<  5) ;// (SSC) Receive Overrun
#define AT91C_SSC_ENDRX           (0x1 <<  6) ;// (SSC) End of Reception
#define AT91C_SSC_RXBUFF          (0x1 <<  7) ;// (SSC) Receive Buffer Full
#define AT91C_SSC_CP0             (0x1 <<  8) ;// (SSC) Compare 0
#define AT91C_SSC_CP1             (0x1 <<  9) ;// (SSC) Compare 1
#define AT91C_SSC_TXSYN           (0x1 << 10) ;// (SSC) Transmit Sync
#define AT91C_SSC_RXSYN           (0x1 << 11) ;// (SSC) Receive Sync
#define AT91C_SSC_TXENA           (0x1 << 16) ;// (SSC) Transmit Enable
#define AT91C_SSC_RXENA           (0x1 << 17) ;// (SSC) Receive Enable
;// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
;// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
;// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR Two-wire Interface
;// *****************************************************************************
;// *** Register offset in AT91S_TWI structure ***
#define TWI_CR          ( 0) ;// Control Register
#define TWI_MMR         ( 4) ;// Master Mode Register
#define TWI_IADR        (12) ;// Internal Address Register
#define TWI_CWGR        (16) ;// Clock Waveform Generator Register
#define TWI_SR          (32) ;// Status Register
#define TWI_IER         (36) ;// Interrupt Enable Register
#define TWI_IDR         (40) ;// Interrupt Disable Register
#define TWI_IMR         (44) ;// Interrupt Mask Register
#define TWI_RHR         (48) ;// Receive Holding Register
#define TWI_THR         (52) ;// Transmit Holding Register
;// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
#define AT91C_TWI_START           (0x1 <<  0) ;// (TWI) Send a START Condition
#define AT91C_TWI_STOP            (0x1 <<  1) ;// (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN            (0x1 <<  2) ;// (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS           (0x1 <<  3) ;// (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SWRST           (0x1 <<  7) ;// (TWI) Software Reset
;// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
#define AT91C_TWI_IADRSZ          (0x3 <<  8) ;// (TWI) Internal Device Address Size
#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) ;// (TWI) No internal device address
#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) ;// (TWI) One-byte internal device address
#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) ;// (TWI) Two-byte internal device address
#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) ;// (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD           (0x1 << 12) ;// (TWI) Master Read Direction
#define AT91C_TWI_DADR            (0x7F << 16) ;// (TWI) Device Address
;// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
#define AT91C_TWI_CLDIV           (0xFF <<  0) ;// (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV           (0xFF <<  8) ;// (TWI) Clock High Divider
#define AT91C_TWI_CKDIV           (0x7 << 16) ;// (TWI) Clock Divider
;// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
#define AT91C_TWI_TXCOMP          (0x1 <<  0) ;// (TWI) Transmission Completed
#define AT91C_TWI_RXRDY           (0x1 <<  1) ;// (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY           (0x1 <<  2) ;// (TWI) Transmit holding register ReaDY
#define AT91C_TWI_OVRE            (0x1 <<  6) ;// (TWI) Overrun Error
#define AT91C_TWI_UNRE            (0x1 <<  7) ;// (TWI) Underrun Error
#define AT91C_TWI_NACK            (0x1 <<  8) ;// (TWI) Not Acknowledged
;// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
;// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
;// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
;// *****************************************************************************
;// *** Register offset in AT91S_PWMC_CH structure ***
#define PWMC_CMR        ( 0) ;// Channel Mode Register
#define PWMC_CDTYR      ( 4) ;// Channel Duty Cycle Register
#define PWMC_CPRDR      ( 8) ;// Channel Period Register
#define PWMC_CCNTR      (12) ;// Channel Counter Register
#define PWMC_CUPDR      (16) ;// Channel Update Register
#define PWMC_Reserved   (20) ;// Reserved
;// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
#define AT91C_PWMC_CPRE           (0xF <<  0) ;// (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
#define 	AT91C_PWMC_CPRE_MCK                  (0x0) ;// (PWMC_CH) 
#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) ;// (PWMC_CH) 
#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) ;// (PWMC_CH) 
#define AT91C_PWMC_CALG           (0x1 <<  8) ;// (PWMC_CH) Channel Alignment
#define AT91C_PWMC_CPOL           (0x1 <<  9) ;// (PWMC_CH) Channel Polarity
#define AT91C_PWMC_CPD            (0x1 << 10) ;// (PWMC_CH) Channel Update Period
;// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
#define AT91C_PWMC_CDTY           (0x0 <<  0) ;// (PWMC_CH) Channel Duty Cycle
;// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
#define AT91C_PWMC_CPRD           (0x0 <<  0) ;// (PWMC_CH) Channel Period
;// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
#define AT91C_PWMC_CCNT           (0x0 <<  0) ;// (PWMC_CH) Channel Counter
;// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
#define AT91C_PWMC_CUPD           (0x0 <<  0) ;// (PWMC_CH) Channel Update

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_PWMC structure ***
#define PWMC_MR         ( 0) ;// PWMC Mode Register
#define PWMC_ENA        ( 4) ;// PWMC Enable Register
#define PWMC_DIS        ( 8) ;// PWMC Disable Register
#define PWMC_SR         (12) ;// PWMC Status Register
#define PWMC_IER        (16) ;// PWMC Interrupt Enable Register
#define PWMC_IDR        (20) ;// PWMC Interrupt Disable Register
#define PWMC_IMR        (24) ;// PWMC Interrupt Mask Register
#define PWMC_ISR        (28) ;// PWMC Interrupt Status Register
#define PWMC_VR         (252) ;// PWMC Version Register
#define PWMC_CH         (512) ;// PWMC Channel
;// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
#define AT91C_PWMC_DIVA           (0xFF <<  0) ;// (PWMC) CLKA divide factor.
#define AT91C_PWMC_PREA           (0xF <<  8) ;// (PWMC) Divider Input Clock Prescaler A
#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) ;// (PWMC) 
#define AT91C_PWMC_DIVB           (0xFF << 16) ;// (PWMC) CLKB divide factor.
#define AT91C_PWMC_PREB           (0xF << 24) ;// (PWMC) Divider Input Clock Prescaler B
#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) ;// (PWMC) 
;// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
#define AT91C_PWMC_CHID0          (0x1 <<  0) ;// (PWMC) Channel ID 0
#define AT91C_PWMC_CHID1          (0x1 <<  1) ;// (PWMC) Channel ID 1
#define AT91C_PWMC_CHID2          (0x1 <<  2) ;// (PWMC) Channel ID 2
#define AT91C_PWMC_CHID3          (0x1 <<  3) ;// (PWMC) Channel ID 3
;// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
;// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
;// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
;// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
;// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
;// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR USB Device Interface
;// *****************************************************************************
;// *** Register offset in AT91S_UDP structure ***
#define UDP_NUM         ( 0) ;// Frame Number Register
#define UDP_GLBSTATE    ( 4) ;// Global State Register
#define UDP_FADDR       ( 8) ;// Function Address Register
#define UDP_IER         (16) ;// Interrupt Enable Register
#define UDP_IDR         (20) ;// Interrupt Disable Register
#define UDP_IMR         (24) ;// Interrupt Mask Register
#define UDP_ISR         (28) ;// Interrupt Status Register
#define UDP_ICR         (32) ;// Interrupt Clear Register
#define UDP_RSTEP       (40) ;// Reset Endpoint Register
#define UDP_CSR         (48) ;// Endpoint Control and Status Register
#define UDP_FDR         (80) ;// Endpoint FIFO Data Register
#define UDP_TXVC        (116) ;// Transceiver Control Register
;// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) ;// (UDP) Frame Number as Defined in the Packet Field Formats
#define AT91C_UDP_FRM_ERR         (0x1 << 16) ;// (UDP) Frame Error
#define AT91C_UDP_FRM_OK          (0x1 << 17) ;// (UDP) Frame OK
;// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
#define AT91C_UDP_FADDEN          (0x1 <<  0) ;// (UDP) Function Address Enable
#define AT91C_UDP_CONFG           (0x1 <<  1) ;// (UDP) Configured
#define AT91C_UDP_ESR             (0x1 <<  2) ;// (UDP) Enable Send Resume
#define AT91C_UDP_RSMINPR         (0x1 <<  3) ;// (UDP) A Resume Has Been Sent to the Host
#define AT91C_UDP_RMWUPE          (0x1 <<  4) ;// (UDP) Remote Wake Up Enable
;// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
#define AT91C_UDP_FADD            (0xFF <<  0) ;// (UDP) Function Address Value
#d