📄 at91sam7x256_inc.h
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;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_PITC structure ***
#define PITC_PIMR ( 0) ;// Period Interval Mode Register
#define PITC_PISR ( 4) ;// Period Interval Status Register
#define PITC_PIVR ( 8) ;// Period Interval Value Register
#define PITC_PIIR (12) ;// Period Interval Image Register
;// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
#define AT91C_PITC_PIV (0xFFFFF << 0) ;// (PITC) Periodic Interval Value
#define AT91C_PITC_PITEN (0x1 << 24) ;// (PITC) Periodic Interval Timer Enabled
#define AT91C_PITC_PITIEN (0x1 << 25) ;// (PITC) Periodic Interval Timer Interrupt Enable
;// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
#define AT91C_PITC_PITS (0x1 << 0) ;// (PITC) Periodic Interval Timer Status
;// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
#define AT91C_PITC_CPIV (0xFFFFF << 0) ;// (PITC) Current Periodic Interval Value
#define AT91C_PITC_PICNT (0xFFF << 20) ;// (PITC) Periodic Interval Counter
;// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_WDTC structure ***
#define WDTC_WDCR ( 0) ;// Watchdog Control Register
#define WDTC_WDMR ( 4) ;// Watchdog Mode Register
#define WDTC_WDSR ( 8) ;// Watchdog Status Register
;// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
#define AT91C_WDTC_WDRSTT (0x1 << 0) ;// (WDTC) Watchdog Restart
#define AT91C_WDTC_KEY (0xFF << 24) ;// (WDTC) Watchdog KEY Password
;// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
#define AT91C_WDTC_WDV (0xFFF << 0) ;// (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDFIEN (0x1 << 12) ;// (WDTC) Watchdog Fault Interrupt Enable
#define AT91C_WDTC_WDRSTEN (0x1 << 13) ;// (WDTC) Watchdog Reset Enable
#define AT91C_WDTC_WDRPROC (0x1 << 14) ;// (WDTC) Watchdog Timer Restart
#define AT91C_WDTC_WDDIS (0x1 << 15) ;// (WDTC) Watchdog Disable
#define AT91C_WDTC_WDD (0xFFF << 16) ;// (WDTC) Watchdog Delta Value
#define AT91C_WDTC_WDDBGHLT (0x1 << 28) ;// (WDTC) Watchdog Debug Halt
#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) ;// (WDTC) Watchdog Idle Halt
;// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
#define AT91C_WDTC_WDUNF (0x1 << 0) ;// (WDTC) Watchdog Underflow
#define AT91C_WDTC_WDERR (0x1 << 1) ;// (WDTC) Watchdog Error
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_VREG structure ***
#define VREG_MR ( 0) ;// Voltage Regulator Mode Register
;// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
#define AT91C_VREG_PSTDBY (0x1 << 0) ;// (VREG) Voltage Regulator Power Standby Mode
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Memory Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_MC structure ***
#define MC_RCR ( 0) ;// MC Remap Control Register
#define MC_ASR ( 4) ;// MC Abort Status Register
#define MC_AASR ( 8) ;// MC Abort Address Status Register
#define MC_FMR (96) ;// MC Flash Mode Register
#define MC_FCR (100) ;// MC Flash Command Register
#define MC_FSR (104) ;// MC Flash Status Register
;// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
#define AT91C_MC_RCB (0x1 << 0) ;// (MC) Remap Command Bit
;// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
#define AT91C_MC_UNDADD (0x1 << 0) ;// (MC) Undefined Addess Abort Status
#define AT91C_MC_MISADD (0x1 << 1) ;// (MC) Misaligned Addess Abort Status
#define AT91C_MC_ABTSZ (0x3 << 8) ;// (MC) Abort Size Status
#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) ;// (MC) Byte
#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) ;// (MC) Half-word
#define AT91C_MC_ABTSZ_WORD (0x2 << 8) ;// (MC) Word
#define AT91C_MC_ABTTYP (0x3 << 10) ;// (MC) Abort Type Status
#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) ;// (MC) Data Read
#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) ;// (MC) Data Write
#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) ;// (MC) Code Fetch
#define AT91C_MC_MST0 (0x1 << 16) ;// (MC) Master 0 Abort Source
#define AT91C_MC_MST1 (0x1 << 17) ;// (MC) Master 1 Abort Source
#define AT91C_MC_SVMST0 (0x1 << 24) ;// (MC) Saved Master 0 Abort Source
#define AT91C_MC_SVMST1 (0x1 << 25) ;// (MC) Saved Master 1 Abort Source
;// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
#define AT91C_MC_FRDY (0x1 << 0) ;// (MC) Flash Ready
#define AT91C_MC_LOCKE (0x1 << 2) ;// (MC) Lock Error
#define AT91C_MC_PROGE (0x1 << 3) ;// (MC) Programming Error
#define AT91C_MC_NEBP (0x1 << 7) ;// (MC) No Erase Before Programming
#define AT91C_MC_FWS (0x3 << 8) ;// (MC) Flash Wait State
#define AT91C_MC_FWS_0FWS (0x0 << 8) ;// (MC) 1 cycle for Read, 2 for Write operations
#define AT91C_MC_FWS_1FWS (0x1 << 8) ;// (MC) 2 cycles for Read, 3 for Write operations
#define AT91C_MC_FWS_2FWS (0x2 << 8) ;// (MC) 3 cycles for Read, 4 for Write operations
#define AT91C_MC_FWS_3FWS (0x3 << 8) ;// (MC) 4 cycles for Read, 4 for Write operations
#define AT91C_MC_FMCN (0xFF << 16) ;// (MC) Flash Microsecond Cycle Number
;// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
#define AT91C_MC_FCMD (0xF << 0) ;// (MC) Flash Command
#define AT91C_MC_FCMD_START_PROG (0x1) ;// (MC) Starts the programming of th epage specified by PAGEN.
#define AT91C_MC_FCMD_LOCK (0x2) ;// (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) ;// (MC) The lock sequence automatically happens after the programming sequence is completed.
#define AT91C_MC_FCMD_UNLOCK (0x4) ;// (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
#define AT91C_MC_FCMD_ERASE_ALL (0x8) ;// (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
#define AT91C_MC_FCMD_SET_GP_NVM (0xB) ;// (MC) Set General Purpose NVM bits.
#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) ;// (MC) Clear General Purpose NVM bits.
#define AT91C_MC_FCMD_SET_SECURITY (0xF) ;// (MC) Set Security Bit.
#define AT91C_MC_PAGEN (0x3FF << 8) ;// (MC) Page Number
#define AT91C_MC_KEY (0xFF << 24) ;// (MC) Writing Protect Key
;// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
#define AT91C_MC_SECURITY (0x1 << 4) ;// (MC) Security Bit Status
#define AT91C_MC_GPNVM0 (0x1 << 8) ;// (MC) Sector 0 Lock Status
#define AT91C_MC_GPNVM1 (0x1 << 9) ;// (MC) Sector 1 Lock Status
#define AT91C_MC_GPNVM2 (0x1 << 10) ;// (MC) Sector 2 Lock Status
#define AT91C_MC_GPNVM3 (0x1 << 11) ;// (MC) Sector 3 Lock Status
#define AT91C_MC_GPNVM4 (0x1 << 12) ;// (MC) Sector 4 Lock Status
#define AT91C_MC_GPNVM5 (0x1 << 13) ;// (MC) Sector 5 Lock Status
#define AT91C_MC_GPNVM6 (0x1 << 14) ;// (MC) Sector 6 Lock Status
#define AT91C_MC_GPNVM7 (0x1 << 15) ;// (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS0 (0x1 << 16) ;// (MC) Sector 0 Lock Status
#define AT91C_MC_LOCKS1 (0x1 << 17) ;// (MC) Sector 1 Lock Status
#define AT91C_MC_LOCKS2 (0x1 << 18) ;// (MC) Sector 2 Lock Status
#define AT91C_MC_LOCKS3 (0x1 << 19) ;// (MC) Sector 3 Lock Status
#define AT91C_MC_LOCKS4 (0x1 << 20) ;// (MC) Sector 4 Lock Status
#define AT91C_MC_LOCKS5 (0x1 << 21) ;// (MC) Sector 5 Lock Status
#define AT91C_MC_LOCKS6 (0x1 << 22) ;// (MC) Sector 6 Lock Status
#define AT91C_MC_LOCKS7 (0x1 << 23) ;// (MC) Sector 7 Lock Status
#define AT91C_MC_LOCKS8 (0x1 << 24) ;// (MC) Sector 8 Lock Status
#define AT91C_MC_LOCKS9 (0x1 << 25) ;// (MC) Sector 9 Lock Status
#define AT91C_MC_LOCKS10 (0x1 << 26) ;// (MC) Sector 10 Lock Status
#define AT91C_MC_LOCKS11 (0x1 << 27) ;// (MC) Sector 11 Lock Status
#define AT91C_MC_LOCKS12 (0x1 << 28) ;// (MC) Sector 12 Lock Status
#define AT91C_MC_LOCKS13 (0x1 << 29) ;// (MC) Sector 13 Lock Status
#define AT91C_MC_LOCKS14 (0x1 << 30) ;// (MC) Sector 14 Lock Status
#define AT91C_MC_LOCKS15 (0x1 << 31) ;// (MC) Sector 15 Lock Status
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Serial Parallel Interface
;// *****************************************************************************
;// *** Register offset in AT91S_SPI structure ***
#define SPI_CR ( 0) ;// Control Register
#define SPI_MR ( 4) ;// Mode Register
#define SPI_RDR ( 8) ;// Receive Data Register
#define SPI_TDR (12) ;// Transmit Data Register
#define SPI_SR (16) ;// Status Register
#define SPI_IER (20) ;// Interrupt Enable Register
#define SPI_IDR (24) ;// Interrupt Disable Register
#define SPI_IMR (28) ;// Interrupt Mask Register
#define SPI_CSR (48) ;// Chip Select Register
#define SPI_RPR (256) ;// Receive Pointer Register
#define SPI_RCR (260) ;// Receive Counter Register
#define SPI_TPR (264) ;// Transmit Pointer Register
#define SPI_TCR (268) ;// Transmit Counter Register
#define SPI_RNPR (272) ;// Receive Next Pointer Register
#define SPI_RNCR (276) ;// Receive Next Counter Register
#define SPI_TNPR (280) ;// Transmit Next Pointer Register
#define SPI_TNCR (284) ;// Transmit Next Counter Register
#define SPI_PTCR (288) ;// PDC Transfer Control Register
#define SPI_PTSR (292) ;// PDC Transfer Status Register
;// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
#define AT91C_SPI_SPIEN (0x1 << 0) ;// (SPI) SPI Enable
#define AT91C_SPI_SPIDIS (0x1 << 1) ;// (SPI) SPI Disable
#define AT91C_SPI_SWRST (0x1 << 7) ;// (SPI) SPI Software reset
#define AT91C_SPI_LASTXFER (0x1 << 24) ;// (SPI) SPI Last Transfer
;// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
#define AT91C_SPI_MSTR (0x1 << 0) ;// (SPI) Master/Slave Mode
#define AT91C_SPI_PS (0x1 << 1) ;// (SPI) Peripheral Select
#define AT91C_SPI_PS_FIXED (0x0 << 1) ;// (SPI) Fixed Peripheral Select
#define AT91C_SPI_PS_VARIABLE (0x1 << 1) ;// (SPI) Variable Peripheral Select
#define AT91C_SPI_PCSDEC (0x1 << 2) ;// (SPI) Chip Select Decode
#define AT91C_SPI_FDIV (0x1 << 3) ;// (SPI) Clock Selection
#define AT91C_SPI_MODFDIS (0x1 << 4) ;// (SPI) Mode Fault Detection
#define AT91C_SPI_LLB (0x1 << 7) ;// (SPI) Clock Selection
#define AT91C_SPI_PCS (0xF << 16) ;// (SPI) Peripheral Chip Select
#define AT91C_SPI_DLYBCS (0xFF << 24) ;// (SPI) Delay Between Chip Selects
;// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
#define AT91C_SPI_RD (0xFFFF << 0) ;// (SPI) Receive Data
#define AT91C_SPI_RPCS (0xF << 16) ;// (SPI) Peripheral Chip Select Status
;// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
#define AT91C_SPI_TD (0xFFFF << 0) ;// (SPI) Transmit Data
#define AT91C_SPI_TPCS (0xF << 16) ;// (SPI) Peripheral Chip Select Status
;// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
#define AT91C_SPI_RDRF (0x1 << 0) ;// (SPI) Receive Data Register Full
#define AT91C_SPI_TDRE (0x1 << 1) ;// (SPI) Transmit Data Register Empty
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