📄 at91sam7x256_inc.h
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;// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
#define AT91C_US_FORCE_NTRST (0x1 << 0) ;// (DBGU) Force NTRST in JTAG
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
;// *****************************************************************************
;// *** Register offset in AT91S_PIO structure ***
#define PIO_PER ( 0) ;// PIO Enable Register
#define PIO_PDR ( 4) ;// PIO Disable Register
#define PIO_PSR ( 8) ;// PIO Status Register
#define PIO_OER (16) ;// Output Enable Register
#define PIO_ODR (20) ;// Output Disable Registerr
#define PIO_OSR (24) ;// Output Status Register
#define PIO_IFER (32) ;// Input Filter Enable Register
#define PIO_IFDR (36) ;// Input Filter Disable Register
#define PIO_IFSR (40) ;// Input Filter Status Register
#define PIO_SODR (48) ;// Set Output Data Register
#define PIO_CODR (52) ;// Clear Output Data Register
#define PIO_ODSR (56) ;// Output Data Status Register
#define PIO_PDSR (60) ;// Pin Data Status Register
#define PIO_IER (64) ;// Interrupt Enable Register
#define PIO_IDR (68) ;// Interrupt Disable Register
#define PIO_IMR (72) ;// Interrupt Mask Register
#define PIO_ISR (76) ;// Interrupt Status Register
#define PIO_MDER (80) ;// Multi-driver Enable Register
#define PIO_MDDR (84) ;// Multi-driver Disable Register
#define PIO_MDSR (88) ;// Multi-driver Status Register
#define PIO_PPUDR (96) ;// Pull-up Disable Register
#define PIO_PPUER (100) ;// Pull-up Enable Register
#define PIO_PPUSR (104) ;// Pull-up Status Register
#define PIO_ASR (112) ;// Select A Register
#define PIO_BSR (116) ;// Select B Register
#define PIO_ABSR (120) ;// AB Select Status Register
#define PIO_OWER (160) ;// Output Write Enable Register
#define PIO_OWDR (164) ;// Output Write Disable Register
#define PIO_OWSR (168) ;// Output Write Status Register
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Clock Generator Controler
;// *****************************************************************************
;// *** Register offset in AT91S_CKGR structure ***
#define CKGR_MOR ( 0) ;// Main Oscillator Register
#define CKGR_MCFR ( 4) ;// Main Clock Frequency Register
#define CKGR_PLLR (12) ;// PLL Register
;// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
#define AT91C_CKGR_MOSCEN (0x1 << 0) ;// (CKGR) Main Oscillator Enable
#define AT91C_CKGR_OSCBYPASS (0x1 << 1) ;// (CKGR) Main Oscillator Bypass
#define AT91C_CKGR_OSCOUNT (0xFF << 8) ;// (CKGR) Main Oscillator Start-up Time
;// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
#define AT91C_CKGR_MAINF (0xFFFF << 0) ;// (CKGR) Main Clock Frequency
#define AT91C_CKGR_MAINRDY (0x1 << 16) ;// (CKGR) Main Clock Ready
;// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
#define AT91C_CKGR_DIV (0xFF << 0) ;// (CKGR) Divider Selected
#define AT91C_CKGR_DIV_0 (0x0) ;// (CKGR) Divider output is 0
#define AT91C_CKGR_DIV_BYPASS (0x1) ;// (CKGR) Divider is bypassed
#define AT91C_CKGR_PLLCOUNT (0x3F << 8) ;// (CKGR) PLL Counter
#define AT91C_CKGR_OUT (0x3 << 14) ;// (CKGR) PLL Output Frequency Range
#define AT91C_CKGR_OUT_0 (0x0 << 14) ;// (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_1 (0x1 << 14) ;// (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_2 (0x2 << 14) ;// (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_OUT_3 (0x3 << 14) ;// (CKGR) Please refer to the PLL datasheet
#define AT91C_CKGR_MUL (0x7FF << 16) ;// (CKGR) PLL Multiplier
#define AT91C_CKGR_USBDIV (0x3 << 28) ;// (CKGR) Divider for USB Clocks
#define AT91C_CKGR_USBDIV_0 (0x0 << 28) ;// (CKGR) Divider output is PLL clock output
#define AT91C_CKGR_USBDIV_1 (0x1 << 28) ;// (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 (0x2 << 28) ;// (CKGR) Divider output is PLL clock output divided by 4
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Power Management Controler
;// *****************************************************************************
;// *** Register offset in AT91S_PMC structure ***
#define PMC_SCER ( 0) ;// System Clock Enable Register
#define PMC_SCDR ( 4) ;// System Clock Disable Register
#define PMC_SCSR ( 8) ;// System Clock Status Register
#define PMC_PCER (16) ;// Peripheral Clock Enable Register
#define PMC_PCDR (20) ;// Peripheral Clock Disable Register
#define PMC_PCSR (24) ;// Peripheral Clock Status Register
#define PMC_MOR (32) ;// Main Oscillator Register
#define PMC_MCFR (36) ;// Main Clock Frequency Register
#define PMC_PLLR (44) ;// PLL Register
#define PMC_MCKR (48) ;// Master Clock Register
#define PMC_PCKR (64) ;// Programmable Clock Register
#define PMC_IER (96) ;// Interrupt Enable Register
#define PMC_IDR (100) ;// Interrupt Disable Register
#define PMC_SR (104) ;// Status Register
#define PMC_IMR (108) ;// Interrupt Mask Register
;// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
#define AT91C_PMC_PCK (0x1 << 0) ;// (PMC) Processor Clock
#define AT91C_PMC_UDP (0x1 << 7) ;// (PMC) USB Device Port Clock
#define AT91C_PMC_PCK0 (0x1 << 8) ;// (PMC) Programmable Clock Output
#define AT91C_PMC_PCK1 (0x1 << 9) ;// (PMC) Programmable Clock Output
#define AT91C_PMC_PCK2 (0x1 << 10) ;// (PMC) Programmable Clock Output
#define AT91C_PMC_PCK3 (0x1 << 11) ;// (PMC) Programmable Clock Output
;// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
;// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
;// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
;// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
;// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
;// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
#define AT91C_PMC_CSS (0x3 << 0) ;// (PMC) Programmable Clock Selection
#define AT91C_PMC_CSS_SLOW_CLK (0x0) ;// (PMC) Slow Clock is selected
#define AT91C_PMC_CSS_MAIN_CLK (0x1) ;// (PMC) Main Clock is selected
#define AT91C_PMC_CSS_PLL_CLK (0x3) ;// (PMC) Clock from PLL is selected
#define AT91C_PMC_PRES (0x7 << 2) ;// (PMC) Programmable Clock Prescaler
#define AT91C_PMC_PRES_CLK (0x0 << 2) ;// (PMC) Selected clock
#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) ;// (PMC) Selected clock divided by 2
#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) ;// (PMC) Selected clock divided by 4
#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) ;// (PMC) Selected clock divided by 8
#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) ;// (PMC) Selected clock divided by 16
#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) ;// (PMC) Selected clock divided by 32
#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) ;// (PMC) Selected clock divided by 64
;// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
;// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
#define AT91C_PMC_MOSCS (0x1 << 0) ;// (PMC) MOSC Status/Enable/Disable/Mask
#define AT91C_PMC_LOCK (0x1 << 2) ;// (PMC) PLL Status/Enable/Disable/Mask
#define AT91C_PMC_MCKRDY (0x1 << 3) ;// (PMC) MCK_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK0RDY (0x1 << 8) ;// (PMC) PCK0_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK1RDY (0x1 << 9) ;// (PMC) PCK1_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK2RDY (0x1 << 10) ;// (PMC) PCK2_RDY Status/Enable/Disable/Mask
#define AT91C_PMC_PCK3RDY (0x1 << 11) ;// (PMC) PCK3_RDY Status/Enable/Disable/Mask
;// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
;// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
;// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Reset Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_RSTC structure ***
#define RSTC_RCR ( 0) ;// Reset Control Register
#define RSTC_RSR ( 4) ;// Reset Status Register
#define RSTC_RMR ( 8) ;// Reset Mode Register
;// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
#define AT91C_RSTC_PROCRST (0x1 << 0) ;// (RSTC) Processor Reset
#define AT91C_RSTC_PERRST (0x1 << 2) ;// (RSTC) Peripheral Reset
#define AT91C_RSTC_EXTRST (0x1 << 3) ;// (RSTC) External Reset
#define AT91C_RSTC_KEY (0xFF << 24) ;// (RSTC) Password
;// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
#define AT91C_RSTC_URSTS (0x1 << 0) ;// (RSTC) User Reset Status
#define AT91C_RSTC_BODSTS (0x1 << 1) ;// (RSTC) Brownout Detection Status
#define AT91C_RSTC_RSTTYP (0x7 << 8) ;// (RSTC) Reset Type
#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) ;// (RSTC) Power-up Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) ;// (RSTC) WakeUp Reset. VDDCORE rising.
#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) ;// (RSTC) Watchdog Reset. Watchdog overflow occured.
#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) ;// (RSTC) Software Reset. Processor reset required by the software.
#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) ;// (RSTC) User Reset. NRST pin detected low.
#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) ;// (RSTC) Brownout Reset occured.
#define AT91C_RSTC_NRSTL (0x1 << 16) ;// (RSTC) NRST pin level
#define AT91C_RSTC_SRCMP (0x1 << 17) ;// (RSTC) Software Reset Command in Progress.
;// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
#define AT91C_RSTC_URSTEN (0x1 << 0) ;// (RSTC) User Reset Enable
#define AT91C_RSTC_URSTIEN (0x1 << 4) ;// (RSTC) User Reset Interrupt Enable
#define AT91C_RSTC_ERSTL (0xF << 8) ;// (RSTC) User Reset Length
#define AT91C_RSTC_BODIEN (0x1 << 16) ;// (RSTC) Brownout Detection Interrupt Enable
;// *****************************************************************************
;// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
;// *****************************************************************************
;// *** Register offset in AT91S_RTTC structure ***
#define RTTC_RTMR ( 0) ;// Real-time Mode Register
#define RTTC_RTAR ( 4) ;// Real-time Alarm Register
#define RTTC_RTVR ( 8) ;// Real-time Value Register
#define RTTC_RTSR (12) ;// Real-time Status Register
;// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
#define AT91C_RTTC_RTPRES (0xFFFF << 0) ;// (RTTC) Real-time Timer Prescaler Value
#define AT91C_RTTC_ALMIEN (0x1 << 16) ;// (RTTC) Alarm Interrupt Enable
#define AT91C_RTTC_RTTINCIEN (0x1 << 17) ;// (RTTC) Real Time Timer Increment Interrupt Enable
#define AT91C_RTTC_RTTRST (0x1 << 18) ;// (RTTC) Real Time Timer Restart
;// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
#define AT91C_RTTC_ALMV (0x0 << 0) ;// (RTTC) Alarm Value
;// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
#define AT91C_RTTC_CRTV (0x0 << 0) ;// (RTTC) Current Real-time Value
;// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
#define AT91C_RTTC_ALMS (0x1 << 0) ;// (RTTC) Real-time Alarm Status
#define AT91C_RTTC_RTTINC (0x1 << 1) ;// (RTTC) Real-time Timer Increment
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