at91sam7x256_inc.h

at91sam7x256的AIC已经编译好

;//  ----------------------------------------------------------------------------
;//          ATMEL Microcontroller Software Support  -  ROUSSET  -
;//  ----------------------------------------------------------------------------
;//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
;//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
;//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
;//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
;//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
;//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
;//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
;//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
;//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;//  ----------------------------------------------------------------------------
;// File Name           : AT91SAM7X256.h
;// Object              : AT91SAM7X256 definitions
;// Generated           : AT91 SW Application Group  09/12/2005 (15:39:14)
;// 
;// CVS Reference       : /AT91SAM7X256.pl/1.14/Mon Sep 12 12:28:34 2005;//
;// CVS Reference       : /SYS_SAM7X.pl/1.3/Wed Feb  2 15:48:15 2005;//
;// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005;//
;// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 14:00:19 2005;//
;// CVS Reference       : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005;//
;// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 12:39:23 2005;//
;// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005;//
;// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005;//
;// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005;//
;// CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004;//
;// CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004;//
;// CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004;//
;// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:40:38 2005;//
;// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005;//
;// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005;//
;// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005;//
;// CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005;//
;// CVS Reference       : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005;//
;// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004;//
;// CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005;//
;// CVS Reference       : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005;//
;// CVS Reference       : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005;//
;// CVS Reference       : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005;//
;// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:46:08 2005;//
;// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005;//
;//  ----------------------------------------------------------------------------

;// Hardware register definition

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR System Peripherals
;// *****************************************************************************

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
;// *****************************************************************************
;// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR         ( 0) ;// Source Mode Register
#define AIC_SVR         (128) ;// Source Vector Register
#define AIC_IVR         (256) ;// IRQ Vector Register
#define AIC_FVR         (260) ;// FIQ Vector Register
#define AIC_ISR         (264) ;// Interrupt Status Register
#define AIC_IPR         (268) ;// Interrupt Pending Register
#define AIC_IMR         (272) ;// Interrupt Mask Register
#define AIC_CISR        (276) ;// Core Interrupt Status Register
#define AIC_IECR        (288) ;// Interrupt Enable Command Register
#define AIC_IDCR        (292) ;// Interrupt Disable Command Register
#define AIC_ICCR        (296) ;// Interrupt Clear Command Register
#define AIC_ISCR        (300) ;// Interrupt Set Command Register
#define AIC_EOICR       (304) ;// End of Interrupt Command Register
#define AIC_SPU         (308) ;// Spurious Vector Register
#define AIC_DCR         (312) ;// Debug Control Register (Protect)
#define AIC_FFER        (320) ;// Fast Forcing Enable Register
#define AIC_FFDR        (324) ;// Fast Forcing Disable Register
#define AIC_FFSR        (328) ;// Fast Forcing Status Register
;// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
#define AT91C_AIC_PRIOR           (0x7 <<  0) ;// (AIC) Priority Level
#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) ;// (AIC) Lowest priority level
#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) ;// (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE         (0x3 <<  5) ;// (AIC) Interrupt Source Type
#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) ;// (AIC) External Sources Code Label Low-level Sensitive
#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) ;// (AIC) Internal Sources Code Label High-level Sensitive
#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) ;// (AIC) Internal Sources Code Label Positive Edge triggered
#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) ;// (AIC) External Sources Code Label Negative Edge triggered
#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) ;// (AIC) Internal Or External Sources Code Label High-level Sensitive
#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) ;// (AIC) Internal Or External Sources Code Label Positive Edge triggered
;// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
#define AT91C_AIC_NFIQ            (0x1 <<  0) ;// (AIC) NFIQ Status
#define AT91C_AIC_NIRQ            (0x1 <<  1) ;// (AIC) NIRQ Status
;// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
#define AT91C_AIC_DCR_PROT        (0x1 <<  0) ;// (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) ;// (AIC) General Mask

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
;// *****************************************************************************
;// *** Register offset in AT91S_PDC structure ***
#define PDC_RPR         ( 0) ;// Receive Pointer Register
#define PDC_RCR         ( 4) ;// Receive Counter Register
#define PDC_TPR         ( 8) ;// Transmit Pointer Register
#define PDC_TCR         (12) ;// Transmit Counter Register
#define PDC_RNPR        (16) ;// Receive Next Pointer Register
#define PDC_RNCR        (20) ;// Receive Next Counter Register
#define PDC_TNPR        (24) ;// Transmit Next Pointer Register
#define PDC_TNCR        (28) ;// Transmit Next Counter Register
#define PDC_PTCR        (32) ;// PDC Transfer Control Register
#define PDC_PTSR        (36) ;// PDC Transfer Status Register
;// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
#define AT91C_PDC_RXTEN           (0x1 <<  0) ;// (PDC) Receiver Transfer Enable
#define AT91C_PDC_RXTDIS          (0x1 <<  1) ;// (PDC) Receiver Transfer Disable
#define AT91C_PDC_TXTEN           (0x1 <<  8) ;// (PDC) Transmitter Transfer Enable
#define AT91C_PDC_TXTDIS          (0x1 <<  9) ;// (PDC) Transmitter Transfer Disable
;// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 

;// *****************************************************************************
;//              SOFTWARE API DEFINITION  FOR Debug Unit
;// *****************************************************************************
;// *** Register offset in AT91S_DBGU structure ***
#define DBGU_CR         ( 0) ;// Control Register
#define DBGU_MR         ( 4) ;// Mode Register
#define DBGU_IER        ( 8) ;// Interrupt Enable Register
#define DBGU_IDR        (12) ;// Interrupt Disable Register
#define DBGU_IMR        (16) ;// Interrupt Mask Register
#define DBGU_CSR        (20) ;// Channel Status Register
#define DBGU_RHR        (24) ;// Receiver Holding Register
#define DBGU_THR        (28) ;// Transmitter Holding Register
#define DBGU_BRGR       (32) ;// Baud Rate Generator Register
#define DBGU_CIDR       (64) ;// Chip ID Register
#define DBGU_EXID       (68) ;// Chip ID Extension Register
#define DBGU_FNTR       (72) ;// Force NTRST Register
#define DBGU_RPR        (256) ;// Receive Pointer Register
#define DBGU_RCR        (260) ;// Receive Counter Register
#define DBGU_TPR        (264) ;// Transmit Pointer Register
#define DBGU_TCR        (268) ;// Transmit Counter Register
#define DBGU_RNPR       (272) ;// Receive Next Pointer Register
#define DBGU_RNCR       (276) ;// Receive Next Counter Register
#define DBGU_TNPR       (280) ;// Transmit Next Pointer Register
#define DBGU_TNCR       (284) ;// Transmit Next Counter Register
#define DBGU_PTCR       (288) ;// PDC Transfer Control Register
#define DBGU_PTSR       (292) ;// PDC Transfer Status Register
;// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
#define AT91C_US_RSTRX            (0x1 <<  2) ;// (DBGU) Reset Receiver
#define AT91C_US_RSTTX            (0x1 <<  3) ;// (DBGU) Reset Transmitter
#define AT91C_US_RXEN             (0x1 <<  4) ;// (DBGU) Receiver Enable
#define AT91C_US_RXDIS            (0x1 <<  5) ;// (DBGU) Receiver Disable
#define AT91C_US_TXEN             (0x1 <<  6) ;// (DBGU) Transmitter Enable
#define AT91C_US_TXDIS            (0x1 <<  7) ;// (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA           (0x1 <<  8) ;// (DBGU) Reset Status Bits
;// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
#define AT91C_US_PAR              (0x7 <<  9) ;// (DBGU) Parity type
#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) ;// (DBGU) Even Parity
#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) ;// (DBGU) Odd Parity
#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) ;// (DBGU) Parity forced to 0 (Space)
#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) ;// (DBGU) Parity forced to 1 (Mark)
#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) ;// (DBGU) No Parity
#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) ;// (DBGU) Multi-drop mode
#define AT91C_US_CHMODE           (0x3 << 14) ;// (DBGU) Channel Mode
#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) ;// (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) ;// (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) ;// (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) ;// (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
;// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
#define AT91C_US_RXRDY            (0x1 <<  0) ;// (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY            (0x1 <<  1) ;// (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX            (0x1 <<  3) ;// (DBGU) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX            (0x1 <<  4) ;// (DBGU) End of Transmit Interrupt
#define AT91C_US_OVRE             (0x1 <<  5) ;// (DBGU) Overrun Interrupt
#define AT91C_US_FRAME            (0x1 <<  6) ;// (DBGU) Framing Error Interrupt
#define AT91C_US_PARE             (0x1 <<  7) ;// (DBGU) Parity Error Interrupt
#define AT91C_US_TXEMPTY          (0x1 <<  9) ;// (DBGU) TXEMPTY Interrupt
#define AT91C_US_TXBUFE           (0x1 << 11) ;// (DBGU) TXBUFE Interrupt
#define AT91C_US_RXBUFF           (0x1 << 12) ;// (DBGU) RXBUFF Interrupt
#define AT91C_US_COMM_TX          (0x1 << 30) ;// (DBGU) COMM_TX Interrupt
#define AT91C_US_COMM_RX          (0x1 << 31) ;// (DBGU) COMM_RX Interrupt
;// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
;// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
;// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------