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📄 os_cpu_a.lst

📁 at91sam7x256的TC已经编译好
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###############################################################################
#                                                                             #
#     IAR Systems ARM Assembler V4.42A/W32 28/Feb/2008  10:18:19              #
#     Copyright 1999-2007 IAR Systems. All rights reserved.                   #
#                                                                             #
#           Source file   =  D:\Graduate_Designed\uCOS_study\uCOS_II\Ports\os_cpu_a.asm#
#           List file     =  D:\Graduate_Designed\uCOS_study\Compil\BINARY\List\os_cpu_a.lst#
#           Object file   =  D:\Graduate_Designed\uCOS_study\Compil\BINARY\Obj\os_cpu_a.r79#
#           Command line  =  D:\Graduate_Designed\uCOS_study\uCOS_II\Ports\os_cpu_a.asm #
#                            -OD:\Graduate_Designed\uCOS_study\Compil\BINARY\Obj\ #
#                            -s+ -M<> -w+ -r                                  #
#                            -LD:\Graduate_Designed\uCOS_study\Compil\BINARY\List\ #
#                            -t8 --cpu ARM7TDMI --fpu None                    #
#                            -IE:\ProgramFiles\IAR Systems\Embedded Workbench 4.0 Evaluation\arm\INC\ #
#                            -ID:\Graduate_Designed\uCOS_study\Compil\..\INC\ #
#                            -ID:\Graduate_Designed\uCOS_study\Compil\..\uCOS_II\Ports\ #
#                                                                             #
###############################################################################

    1    00000000              ;***********************************************
                               ************************************************
                               *********
    2    00000000              ;                                              
                                uC/OS-II
    3    00000000              ;                                         The
                                Real-Time Kernel
    4    00000000              ;
    5    00000000              ;                               (c) Copyright
                                1992-2005, Micrium, Weston, FL
    6    00000000              ;                                          All
                                Rights Reserved
    7    00000000              ;
    8    00000000              ;                                          
                                Generic ARM Port
    9    00000000              ;
   10    00000000              ; File      : OS_CPU_A.ASM
   11    00000000              ; Version   : V1.61
   12    00000000              ; By        : Jean J. Labrosse
   13    00000000              ;
   14    00000000              ; For       : ARM7 or ARM9
   15    00000000              ; Mode      : ARM or Thumb
   16    00000000              ; Toolchain : IAR's EWARM V4.11a and higher
   17    00000000              ;***********************************************
                               ************************************************
                               *********
   18    00000000              
   19    00000000                          EXTERN  OSRunning                   
  ; External references
   20    00000000                          EXTERN  OSPrioCur
   21    00000000                          EXTERN  OSPrioHighRdy
   22    00000000                          EXTERN  OSTCBCur
   23    00000000                          EXTERN  OSTCBHighRdy
   24    00000000                          EXTERN  OSIntNesting
   25    00000000                          EXTERN  OSIntExit
   26    00000000                          EXTERN  OSTaskSwHook
   27    00000000                          EXTERN  OS_CPU_IRQ_ISR_Handler
   28    00000000                          EXTERN  OS_CPU_FIQ_ISR_Handler
   29    00000000              
   30    00000000              
   31    00000000                          PUBLIC  OS_CPU_SR_Save              
  ; Functions declared in this file
   32    00000000                          PUBLIC  OS_CPU_SR_Restore
   33    00000000                          PUBLIC  OSStartHighRdy
   34    00000000                          PUBLIC  OSCtxSw
   35    00000000                          PUBLIC  OSIntCtxSw
   36    00000000                          PUBLIC  OS_CPU_IRQ_ISR
   37    00000000                          PUBLIC  OS_CPU_FIQ_ISR
   38    00000000              
   39    00000000              
   40    000000C0              NO_INT      EQU     0xC0                        
                                ; Mask used to disable interrupts (Both FIR and
                                IRQ)
   41    00000013              SVC32_MODE  EQU     0x13
   42    00000011              FIQ32_MODE  EQU     0x11
   43    00000012              IRQ32_MODE  EQU     0x12
   44    00000000              
   45    00000000              
   46    00000000              ;***********************************************
                               ************************************************
                               **********
   47    00000000              ;                                   CRITICAL
                                SECTION METHOD 3 FUNCTIONS
   48    00000000              ;
   49    00000000              ; Description: Disable/Enable interrupts by
                                preserving the state of interrupts.  Generally
                                speaking you
   50    00000000              ;              would store the state of the
                                interrupt disable flag in the local variable
                                'cpu_sr' and then
   51    00000000              ;              disable interrupts.  'cpu_sr' is
                                allocated in all of uC/OS-II's functions that
                                need to
   52    00000000              ;              disable interrupts.  You would
                                restore the interrupt disable state by copying
                                back 'cpu_sr'
   53    00000000              ;              into the CPU's status register.
   54    00000000              ;
   55    00000000              ; Prototypes :     OS_CPU_SR  OS_CPU_SR_Save(voi
                               d);
   56    00000000              ;                  void       OS_CPU_SR_Restore(
                               OS_CPU_SR cpu_sr);
   57    00000000              ;
   58    00000000              ;
   59    00000000              ; Note(s)    : 1) These functions are used in
                                general like this:
   60    00000000              ;
   61    00000000              ;                 void Task (void *p_arg)
   62    00000000              ;                 {
   63    00000000              ;                 #if OS_CRITICAL_METHOD == 3   
                                      /* Allocate storage for CPU status
                                register */
   64    00000000              ;                     OS_CPU_SR  cpu_sr;
   65    00000000              ;                 #endif
   66    00000000              ;
   67    00000000              ;                          :
   68    00000000              ;                          :
   69    00000000              ;                     OS_ENTER_CRITICAL();      
                                      /* cpu_sr = OS_CPU_SaveSR();             
                                  */
   70    00000000              ;                          :
   71    00000000              ;                          :
   72    00000000              ;                     OS_EXIT_CRITICAL();       
                                      /* OS_CPU_RestoreSR(cpu_sr);             
                                  */
   73    00000000              ;                          :
   74    00000000              ;                          :
   75    00000000              ;                 }
   76    00000000              ;
   77    00000000              ;              2) OS_CPU_SaveSR() is implemented
                                as recommended by Atmel's application
                                note:
   78    00000000              ;
   79    00000000              ;                    "Disabling Interrupts at
                                Processor Level"
   80    00000000              ;***********************************************
                               ************************************************
                               **********
   81    00000000              
   82    00000000                      RSEG CODE:CODE:NOROOT(2)
   83    00000000                      CODE32
   84    00000000              
   85    00000000              OS_CPU_SR_Save
   86    00000000 00000FE1             MRS     R0,CPSR                     ;
                                                   Set IRQ and FIQ bits in CPSR
                                                   to disable all interrupts
   87    00000004 C01080E3             ORR     R1,R0,#NO_INT
   88    00000008 01F021E1             MSR     CPSR_c,R1
   89    0000000C 00100FE1             MRS     R1,CPSR                     ;
                                                   Confirm that CPSR contains
                                                   the proper interrupt disable
                                                   flags
   90    00000010 C01001E2             AND     R1,R1,#NO_INT
   91    00000014 C00051E3             CMP     R1,#NO_INT
   92    00000018 F8FFFF1A             BNE     OS_CPU_SR_Save              ;
  Not properly disabled (try again)
   93    0000001C 1EFF2FE1             BX      LR                          ;
  Disabled, return the original CPSR contents in R0
   94    00000020              
   95    00000020              
   96    00000020              OS_CPU_SR_Restore
   97    00000020 00F021E1             MSR     CPSR_c,R0
   98    00000024 1EFF2FE1             BX      LR
   99    00000028              
  100    00000028              
  101    00000028              ;***********************************************
                               ************************************************
                               **********
  102    00000028              ;                                          START
                                MULTITASKING
  103    00000028              ;                                       void
                                OSStartHighRdy(void)
  104    00000028              ;
  105    00000028              ; Note(s) : 1) OSStartHighRdy() MUST:
  106    00000028              ;              a) Call OSTaskSwHook() then,
  107    00000028              ;              b) Set OSRunning to TRUE,
  108    00000028              ;              c) Switch to the highest priority
                                task.
  109    00000028              ;***********************************************
                               ************************************************
                               **********
  110    00000028              
  111    00000000                      RSEG CODE:CODE:NOROOT(2)
  112    00000000                      CODE32
  113    00000000              
  114    00000000              OSStartHighRdy
  115    00000000              
  116    00000000 ........             LDR     R0, ??OS_TaskSwHook     ;
                                                    OSTaskSwHook();
  117    00000004 0FE0A0E1             MOV     LR, PC
  118    00000008 10FF2FE1             BX      R0
  119    0000000C              
  120    0000000C D3F02FE3             MSR     CPSR_cxsf, #0xD3        ; Switch
                                                           to SVC mode with IRQ
                                                           and FIQ disabled
  121    00000010              
  122    00000010 ........             LDR     R4, ??OS_Running        ;
                                                    OSRunning = TRUE
  123    00000014 0150A0E3             MOV     R5, #1
  124    00000018 0050C4E5             STRB    R5, [R4]
  125    0000001C              
  126    0000001C                                                      ; SWITCH
                                TO HIGHEST PRIORITY TASK
  127    0000001C ........             LDR     R4, ??OS_TCBHighRdy     ;    Get
                                                    highest priority task TCB
                                                    address
  128    00000020 004094E5             LDR     R4, [R4]                ;    get
                                                    stack pointer
  129    00000024 00D094E5             LDR     SP, [R4]                ;   
                                                    switch to the new
                                                    stack
  130    00000028              
  131    00000028 04409DE4             LDR     R4,  [SP], #4           ;    pop
                                                     new task's CPSR
  132    0000002C 04F06FE1             MSR     SPSR_cxsf,R4
  133    00000030 FFDFFDE8             LDMFD   SP!, {R0-R12,LR,PC}^    ;    pop

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