📄 cstartup.lst
字号:
111 00000000
112 00000000 ;// Execution starts here.
113 00000000 ;// After a reset, the mode is ARM, Supervisor,
interrupts disabled.
114 00000000
115 00000000
116 00000000 CODE32
117 00000000 ?cstartup
118 00000000
119 00000000 ;// Add initialization nedded before setup of
stackpointers here
120 00000000 8C009FE5 ldr r0,=0xFFFFFD08
121 00000004 //Reset Mode Register
122 00000004 8C109FE5 ldr r1,=0xa5000001
123 00000008 //No interrupt permitted during
reset
124 00000008 001080E5 str r1,[r0]
125 0000000C
126 00000000 EXTERN AT91F_LowLevelInit
127 0000000C #define RamEnd 0x00210000
128 0000000C 84D9A0E3 ldr r13,=RamEnd
;// temporary stack
in internal
RAM*/
129 00000010 84009FE5 ldr r0,=AT91F_LowLevelInit
130 00000014 0FE0A0E1 mov lr, pc
131 00000018 10FF2FE1 bx r0
132 0000001C //用AT91F_LowLevelInit时，暂时用
RAM最高地址做栈顶。
133 0000001C
134 0000001C ;// Initialize the stack pointers.
135 0000001C ;// The pattern below can be used for any of the
exception stacks:
136 0000001C ;// FIQ, IRQ, SVC, ABT, UND, SYS.
137 0000001C ;// The USR mode uses the same stack as
SYS.
138 0000001C ;// The stack segments must be defined in the
linker command file,
139 0000001C ;// and be declared above.
140 0000001C 00000FE1 mrs r0,cpsr
;//
Original PSR
value
141 00000020 1F00C0E3 bic r0,r0,#MODE_BITS
;// Clear
the mode bits
142 00000024 120080E3 orr r0,r0,#IRQ_MODE
;// Set
IRQ mode bits
143 00000028 00F021E1 msr cpsr_c,r0
;//
Change the
mode
144 0000002C 6CD09FE5 ldr sp,=SFE(IRQ_STACK) &
0xFFFFFFF8 ;//
End of IRQ_STACK
145 00000030
146 00000030 1F00C0E3 bic r0,r0,#MODE_BITS
;// Clear
the mode bits
147 00000034 1F0080E3 orr r0,r0,#SYS_MODE
;// Set
System mode
bits
148 00000038 00F021E1 msr cpsr_c,r0
;//
Change the
mode
149 0000003C 60D09FE5 ldr sp,=SFE(CSTACK) &
0xFFFFFFF8
;// End of
CSTACK
150 00000040
151 00000040 1F00C0E3 bic r0,r0,#MODE_BITS
;// Clear
the mode bits
152 00000044 130080E3 orr r0,r0,#SVC_MODE
;// Set
SVC mode bits
153 00000048 00F021E1 msr cpsr_c,r0
;//
Change the
mode
154 0000004C 54D09FE5 ldr sp,=SFE(SVC_STACK) &
0xFFFFFFF8 ;//
End of CSTACK
155 00000050
156 00000050 ;//init the PLL for fast bootup
157 00000050 54009FE5 ldr r0, =0x00000601
;//PMC_MOR = ((
AT91C_CKGR_OSCOUNT
& (0x06 <<8) |
//0x000006001
158 00000054 54109FE5 ldr r1, =0xFFFFFC20
159 00000058 000081E5 str r0, [r1]
160 0000005C
161 0000005C 50009FE5 ldr r0, =0x00191C05
;//PMC_PLLR =
((AT91C_CKGR_DIV &
0x05) |
162 00000060 50109FE5 ldr r1, =0xFFFFFC2C
;//
(AT91C_CKGR_P
LLCOUNT & (28<<8))
163 00000064 000081E5 str r0, [r1]
;//
(AT91C_CKGR_M
UL & (25<<16)));//
//0x00191c05
164 00000068
165 00000068 0700A0E3 ldr r0, =0x00000007
;//PMC_MCKR =
AT91C_PMC_CSS_PLL_C
LK |
166 0000006C 48109FE5 ldr r1, =0xFFFFFC30
;//
AT91C_PMC_PRES
_CLK_2 ;//
//0x00000007
167 00000070 000081E5 str r0, [r1]
168 00000074
169 00000074 #ifdef __ARMVFP__
179 00000074 #endif
180 00000074
181 00000074 ;// Add more initialization here
182 00000074
183 00000000 EXTERN __segment_init
184 00000000 EXTERN main
185 00000074 ;// Initialize segments.
186 00000074 ;// __segment_init is assumed to use
187 00000074 ;// instruction set and to be reachable by BL
from the ICODE segment
188 00000074 ;// (it is safest to link them in segment
ICODE).
189 00000074 44009FE5 ldr r0,=__segment_init
190 00000078 0FE0A0E1 mov lr, pc
191 0000007C 10FF2FE1 bx r0
192 00000080
193 00000000 PUBLIC __main
194 00000080 ?jump_to_main:
195 00000080 3CE09FE5 ldr lr,=?call_exit
196 00000084 3C009FE5 ldr r0,=main
197 00000088 __main:
198 00000088 10FF2FE1 bx r0
199 0000008C
200 0000008C ;//---------------------------------------------
---------------------------------
201 0000008C ;//- Loop for ever
202 0000008C ;//---------------
203 0000008C ;//- End of application. Normally, never
occur.
204 0000008C ;//- Could jump on Software Reset ( B 0x0
).
205 0000008C ;//---------------------------------------------
---------------------------------
206 0000008C ?call_exit:
207 0000008C End
208 0000008C FEFFFFEA b End
209 00000090
210 00000090 ;// Never return !!
211 00000090 FDFFFFEA b End
212 00000094 ;// Continue to ?main for more IAR specific
system startup
213 00000094
214 00000094
215 00000094
216 00000094 LTORG
216.1 00000094 TABLE
216.2 00000094 08FDFFFF Reference on line 120
216.3 00000098 010000A5 Reference on line 122
216.4 0000009C ........ Reference on line 129
216.5 000000A0 ........ Reference on line 144
216.6 000000A4 ........ Reference on line 149
216.7 000000A8 ........ Reference on line 154
216.8 000000AC 01060000 Reference on line 157
216.9 000000B0 20FCFFFF Reference on line 158
216.10 000000B4 051C1900 Reference on line 161
216.11 000000B8 2CFCFFFF Reference on line 162
216.12 000000BC 30FCFFFF Reference on line 166
216.13 000000C0 ........ Reference on line 189
216.14 000000C4 ........ Reference on line 195
216.15 000000C8 ........ Reference on line 196
216 000000CC LTORG
217 000000CC
218 000000CC ENDMOD
##############################
# CRC:F85B #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 204 #
##############################
##############################
# CRC:F85B #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 204 #
# Modules: 2 #
# Total errors: 0 #
# Total warnings: 0 #
##############################
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