counter.vhd

《精通 Protel DXP 2004 电路设计》

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-- VHDL Counter
-- 2006 3 30 11 6 2
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL Counter
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity Counter Is
  port
  (
    ADD0  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD0
    ADD1  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD1
    ADD2  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD2
    ADD3  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD3
    ADD4  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD4
    ADD5  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD5
    ADD6  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD6
    ADD7  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD7
    ADD8  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD8
    ADD9  : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD9
    ADD10 : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD10
    ADD11 : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD11
    ADD12 : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD12
    ADD13 : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD13
    ADD14 : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD14
    ADD15 : Out   STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ADD15
    CLK   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=CLK
    CLR   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=CLR
    D0    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D0
    D1    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D1
    D2    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D2
    D3    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D3
    D4    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D4
    D5    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D5
    D6    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D6
    D7    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D7
    D8    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D8
    D9    : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D9
    D10   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D10
    D11   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D11
    D12   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D12
    D13   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D13
    D14   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D14
    D15   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=D15
    EDN   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=EDN
    ENP   : In    STD_LOGIC;                                 -- ObjectKind=Port|PrimaryId=ENP
    ENT   : In    STD_LOGIC                                  -- ObjectKind=Port|PrimaryId=ENT
  );
  attribute MacroCell : boolean;

  attribute PinNum : string;
  attribute PinNum of ADD0  : Signal is "1";
  attribute PinNum of ADD1  : Signal is "2";
  attribute PinNum of ADD2  : Signal is "3";
  attribute PinNum of ADD3  : Signal is "4";
  attribute PinNum of ADD4  : Signal is "5";
  attribute PinNum of ADD5  : Signal is "6";
  attribute PinNum of ADD6  : Signal is "7";
  attribute PinNum of ADD7  : Signal is "8";
  attribute PinNum of ADD8  : Signal is "9";
  attribute PinNum of ADD9  : Signal is "10";
  attribute PinNum of ADD10 : Signal is "11";
  attribute PinNum of ADD11 : Signal is "12";
  attribute PinNum of ADD12 : Signal is "13";
  attribute PinNum of ADD13 : Signal is "14";
  attribute PinNum of ADD14 : Signal is "15";
  attribute PinNum of ADD15 : Signal is "16";
  attribute PinNum of CLK   : Signal is "54";
  attribute PinNum of CLR   : Signal is "56";
  attribute PinNum of D0    : Signal is "21";
  attribute PinNum of D1    : Signal is "22";
  attribute PinNum of D2    : Signal is "23";
  attribute PinNum of D3    : Signal is "24";
  attribute PinNum of D4    : Signal is "25";
  attribute PinNum of D5    : Signal is "26";
  attribute PinNum of D6    : Signal is "27";
  attribute PinNum of D7    : Signal is "28";
  attribute PinNum of D8    : Signal is "29";
  attribute PinNum of D9    : Signal is "30";
  attribute PinNum of D10   : Signal is "31";
  attribute PinNum of D11   : Signal is "32";
  attribute PinNum of D12   : Signal is "33";
  attribute PinNum of D13   : Signal is "34";
  attribute PinNum of D14   : Signal is "35";
  attribute PinNum of D15   : Signal is "36";
  attribute PinNum of EDN   : Signal is "41";
  attribute PinNum of ENP   : Signal is "43";
  attribute PinNum of ENT   : Signal is "42";


End Counter;
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architecture structure of Counter is
   Component A_74161                                         -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      port
      (
        A    : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-A
        B    : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-B
        C    : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-C
        CLK  : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-CLK
        CLRN : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-CLRN
        D    : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-D
        ENP  : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-ENP
        ENT  : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-ENT
        LDN  : in  STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-LDN
        QA   : out STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-QA
        QB   : out STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-QB
        QC   : out STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-QC
        QD   : out STD_LOGIC;                                -- ObjectKind=Pin|PrimaryId=U1-QD
        RCO  : out STD_LOGIC                                 -- ObjectKind=Pin|PrimaryId=U1-RCO
      );
   End Component;


    Signal NamedSignal_D0   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D0
    Signal NamedSignal_D1   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D1
    Signal NamedSignal_D10  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D10
    Signal NamedSignal_D11  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D11
    Signal NamedSignal_D12  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D12
    Signal NamedSignal_D13  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D13
    Signal NamedSignal_D14  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D14
    Signal NamedSignal_D15  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D15
    Signal NamedSignal_D2   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D2
    Signal NamedSignal_D3   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D3
    Signal NamedSignal_D4   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D4
    Signal NamedSignal_D5   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D5
    Signal NamedSignal_D6   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D6
    Signal NamedSignal_D7   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D7
    Signal NamedSignal_D8   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D8
    Signal NamedSignal_D9   : STD_LOGIC; -- ObjectKind=Net|PrimaryId=D9
    Signal NamedSignal_ENP  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=ENP
    Signal NamedSignal_ENT  : STD_LOGIC; -- ObjectKind=Net|PrimaryId=ENT