fpga_counter.edf

《精通 Protel DXP 2004 电路设计》

(edif FPGA_Counter_PrjFpg
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap
     (keywordLevel 0)
  )
  (status
    (written
      (timeStamp 2006 3 29 23 47 46)
      (program "Design Explorer DXP - EDIF For PCB"
        (version "1.0.0")
      )
      (author "EDIF For PCB")
    )
  )

  (library COMPONENT_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell A_74161
      (cellType GENERIC)
      (view netListView
        (viewType NETLIST)
        (interface
          (port A    (direction INPUT))
          (port B    (direction INPUT))
          (port C    (direction INPUT))
          (port CLK  (direction INPUT))
          (port CLRN (direction INPUT))
          (port D    (direction INPUT))
          (port ENP  (direction INPUT))
          (port ENT  (direction INPUT))
          (port LDN  (direction INPUT))
          (port QA   (direction OUTPUT))
          (port QB   (direction OUTPUT))
          (port QC   (direction OUTPUT))
          (port QD   (direction OUTPUT))
          (port RCO  (direction OUTPUT))
        )
      )
    )
  )
  (library SHEET_LIB
    (edifLevel 0)
    (technology
      (numberDefinition
        (scale  1  1  (unit  distance))
      )
    )
    (cell Counter_SchDoc
      (cellType generic)
      (view netListView
        (viewType netlist)
        (interface
        )
        (contents
          (Instance U1
            (viewRef NetlistView
              (cellRef A_74161
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "A_74161" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property Footprint (String "" ))
            (Property FPGAVendor (String "Altera" ))
            (Property (rename Library_Name "Library Name") (String "Altera FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "A_74161" ))
            (Property PCB3D (String "" ))
            (Property Published (String "17-Apr-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property UniqueId (String "\FHNLIGCW" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "0" ))
          )
          (Instance U2
            (viewRef NetlistView
              (cellRef A_74161
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "A_74161" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property Footprint (String "" ))
            (Property FPGAVendor (String "Altera" ))
            (Property (rename Library_Name "Library Name") (String "Altera FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "A_74161" ))
            (Property PCB3D (String "" ))
            (Property Published (String "17-Apr-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property UniqueId (String "\CSPUMOLH" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "1" ))
          )
          (Instance U3
            (viewRef NetlistView
              (cellRef A_74161
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "A_74161" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property Footprint (String "" ))
            (Property FPGAVendor (String "Altera" ))
            (Property (rename Library_Name "Library Name") (String "Altera FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "A_74161" ))
            (Property PCB3D (String "" ))
            (Property Published (String "17-Apr-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property UniqueId (String "\TWBVNSPA" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "2" ))
          )
          (Instance U4
            (viewRef NetlistView
              (cellRef A_74161
                (LibraryRef COMPONENT_LIB)
              )
            )
            (Property Comment (String "A_74161" ))
            (Property (rename Component_Kind "Component Kind") (String "Standard" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property Footprint (String "" ))
            (Property FPGAVendor (String "Altera" ))
            (Property (rename Library_Name "Library Name") (String "Altera FPGA.IntLib" ))
            (Property (rename Library_Reference "Library Reference") (String "A_74161" ))
            (Property PCB3D (String "" ))
            (Property Published (String "17-Apr-2002" ))
            (Property Publisher (String "Altium Limited" ))
            (Property (rename Signal_Integrity "Signal Integrity") (String "" ))
            (Property Simulation (String "" ))
            (Property Description (String "4-Bit Binary Up Counter with Synchronous Load and Asynchronous Clear" ))
            (Property UniqueId (String "\NGPEIXDB" ))
            (Property PhysicalPath (String "Counter" ))
            (Property ChannelOffset (String "3" ))
          )
          (Net NetU1_CLK
            (Joined 
                (PortRef CLK (InstanceRef U1))
            )
          )
          (Net NetU1_CLRN
            (Joined 
                (PortRef CLRN (InstanceRef U1))
                (PortRef CLRN (InstanceRef U2))
                (PortRef CLRN (InstanceRef U3))
                (PortRef CLRN (InstanceRef U4))
            )
          )
          (Net NetU1_QA
            (Joined 
                (PortRef QA (InstanceRef U1))
            )
          )
          (Net NetU1_QB
            (Joined 
                (PortRef QB (InstanceRef U1))
            )
          )
          (Net NetU1_QC
            (Joined 
                (PortRef QC (InstanceRef U1))
            )
          )
          (Net NetU1_QD
            (Joined 
                (PortRef QD (InstanceRef U1))
            )
          )
          (Net NetU1_RCO
            (Joined 
                (PortRef RCO (InstanceRef U1))
                (PortRef CLK (InstanceRef U2))
            )
          )
          (Net NetU2_QA
            (Joined 
                (PortRef QA (InstanceRef U2))
            )
          )
          (Net NetU2_QB
            (Joined 
                (PortRef QB (InstanceRef U2))
            )
          )
          (Net NetU2_QC
            (Joined 
                (PortRef QC (InstanceRef U2))
            )
          )
          (Net NetU2_QD
            (Joined 
                (PortRef QD (InstanceRef U2))
            )
          )
          (Net NetU2_RCO
            (Joined 
                (PortRef RCO (InstanceRef U2))
                (PortRef CLK (InstanceRef U3))
            )
          )
          (Net NetU3_QA
            (Joined 
                (PortRef QA (InstanceRef U3))
            )
          )
          (Net NetU3_QB
            (Joined 
                (PortRef QB (InstanceRef U3))
            )
          )
          (Net NetU3_QC
            (Joined 
                (PortRef QC (InstanceRef U3))
            )
          )
          (Net NetU3_QD
            (Joined 
                (PortRef QD (InstanceRef U3))
            )
          )
          (Net NetU3_RCO
            (Joined 
                (PortRef RCO (InstanceRef U3))
                (PortRef CLK (InstanceRef U4))
            )
          )
          (Net NetU4_QA
            (Joined 
                (PortRef QA (InstanceRef U4))
            )
          )
          (Net NetU4_QB
            (Joined 
                (PortRef QB (InstanceRef U4))
            )
          )
          (Net NetU4_QC
            (Joined 
                (PortRef QC (InstanceRef U4))
            )
          )
          (Net NetU4_QD
            (Joined 
                (PortRef QD (InstanceRef U4))
            )
          )
          (Net LDN
            (Joined 
                (PortRef LDN (InstanceRef U1))
                (PortRef LDN (InstanceRef U2))
                (PortRef LDN (InstanceRef U3))
                (PortRef LDN (InstanceRef U4))
            )
          )
          (Net ENT
            (Joined 
                (PortRef ENT (InstanceRef U1))
                (PortRef ENT (InstanceRef U2))
                (PortRef ENT (InstanceRef U3))
                (PortRef ENT (InstanceRef U4))
            )
          )
          (Net ENP
            (Joined 
                (PortRef ENP (InstanceRef U1))
                (PortRef ENP (InstanceRef U2))
                (PortRef ENP (InstanceRef U3))
                (PortRef ENP (InstanceRef U4))
            )
          )
          (Net D15
            (Joined 
                (PortRef D (InstanceRef U4))
            )
          )
          (Net D14
            (Joined 
                (PortRef C (InstanceRef U4))
            )
          )
          (Net D13
            (Joined 
                (PortRef B (InstanceRef U4))
            )
          )
          (Net D12
            (Joined 
                (PortRef A (InstanceRef U4))
            )
          )
          (Net D11
            (Joined 
                (PortRef D (InstanceRef U3))
            )
          )
          (Net D10
            (Joined 
                (PortRef C (InstanceRef U3))
            )
          )
          (Net D9
            (Joined 
                (PortRef B (InstanceRef U3))
            )
          )
          (Net D8
            (Joined 
                (PortRef A (InstanceRef U3))
            )
          )
          (Net D7
            (Joined 
                (PortRef D (InstanceRef U2))
            )
          )
          (Net D6
            (Joined 
                (PortRef C (InstanceRef U2))
            )
          )
          (Net D5
            (Joined 
                (PortRef B (InstanceRef U2))
            )
          )
          (Net D4
            (Joined 
                (PortRef A (InstanceRef U2))
            )
          )
          (Net D3
            (Joined 
                (PortRef D (InstanceRef U1))
            )
          )
          (Net D2
            (Joined 
                (PortRef C (InstanceRef U1))
            )
          )
          (Net D1
            (Joined 
                (PortRef B (InstanceRef U1))
            )
          )
          (Net D0
            (Joined 
                (PortRef A (InstanceRef U1))
            )
          )
       )
     )
   )
  )
  (design FPGA_Counter_PrjFpg
    (cellRef Counter_SchDoc
      (libraryRef SHEET_LIB)
    )
  )
)