bcd8.vhd

《精通 Protel DXP 2004 电路设计》

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-- VHDL BCD8
-- 2006 4 2 15 14 36
-- Created By "DXP VHDL Generator"
-- "Copyright (c) 2002-2004 Altium Limited"
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-- VHDL BCD8
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Library IEEE;
Use     IEEE.std_logic_1164.all;

Entity BCD_Counter Is
  port
  (
    CLEAR  : In    STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=CLEAR
    CLOCK  : In    STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=CLOCK
    ENABLE : In    STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=ENABLE
    LOWER  : Out   STD_LOGIC_VECTOR(3 downto 0);             -- ObjectKind=Port|PrimaryId=LOWER[3..0]
    PARITY : Out   STD_LOGIC;                                -- ObjectKind=Port|PrimaryId=PARITY
    UPPER  : Out   STD_LOGIC_VECTOR(3 downto 0);             -- ObjectKind=Port|PrimaryId=UPPER[3..0]
    URCO   : Out   STD_LOGIC                                 -- ObjectKind=Port|PrimaryId=URCO
  );
  attribute MacroCell : boolean;

End BCD_Counter;
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architecture structure of BCD_Counter is
   Component BCD                                             -- ObjectKind=Sheet Symbol|PrimaryId=H1
      port
      (
        CLEAR  : in  STD_LOGIC;                              -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-CLEAR
        CLOCK  : in  STD_LOGIC;                              -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-CLOCK
        ENABLE : in  STD_LOGIC;                              -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-ENABLE
        OCD    : out STD_LOGIC_VECTOR(3 downto 0);           -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-OCD[3..0]
        RCO    : out STD_LOGIC                               -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-RCO
      );
   End Component;

   Component BUFGS                                           -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      port
      (
        I : in  STD_LOGIC;                                   -- ObjectKind=Pin|PrimaryId=U1-I
        O : out STD_LOGIC                                    -- ObjectKind=Pin|PrimaryId=U1-O
      );
   End Component;

   Component PARITYC                                         -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      port
      (
        L : in  STD_LOGIC_VECTOR(3 downto 0);                -- ObjectKind=Pin|PrimaryId=U2-L[3..0]
        P : out STD_LOGIC;                                   -- ObjectKind=Pin|PrimaryId=U2-P
        U : in  STD_LOGIC_VECTOR(3 downto 0)                 -- ObjectKind=Pin|PrimaryId=U2-U[3..0]
      );
   End Component;


    Signal PinSignal_U1_O    : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU1_O
    Signal PinSignal_U2_L    : STD_LOGIC_VECTOR(3 downto 0); -- ObjectKind=Net|PrimaryId=LOWER[3..0]
    Signal PinSignal_U2_P    : STD_LOGIC; -- ObjectKind=Net|PrimaryId=NetU2_P
    Signal PinSignal_U2_U    : STD_LOGIC_VECTOR(3 downto 0); -- ObjectKind=Net|PrimaryId=UPPER[3..0]

begin
    H2 : BCD                                                 -- ObjectKind=Sheet Symbol|PrimaryId=H2
      Port Map
      (
        CLEAR => CLEAR,                                      -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-CLEAR
        CLOCK => PinSignal_U1_O                              -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-CLOCK
      );

    H1 : BCD                                                 -- ObjectKind=Sheet Symbol|PrimaryId=H1
      Port Map
      (
        CLEAR  => CLEAR,                                     -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-CLEAR
        CLOCK  => PinSignal_U1_O,                            -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-CLOCK
        ENABLE => ENABLE                                     -- ObjectKind=Sheet Entry|PrimaryId=Bcd.vhd-ENABLE
      );

    U2 : PARITYC                                             -- ObjectKind=Part|PrimaryId=U2|SecondaryId=1
      Port Map
      (
        L => PinSignal_U2_L,                                 -- ObjectKind=Pin|PrimaryId=U2-L[3..0]
        P => PinSignal_U2_P,                                 -- ObjectKind=Pin|PrimaryId=U2-P
        U => PinSignal_U2_U                                  -- ObjectKind=Pin|PrimaryId=U2-U[3..0]
      );

    U1 : BUFGS                                               -- ObjectKind=Part|PrimaryId=U1|SecondaryId=1
      Port Map
      (
        I => CLOCK,                                          -- ObjectKind=Pin|PrimaryId=U1-I
        O => PinSignal_U1_O                                  -- ObjectKind=Pin|PrimaryId=U1-O
      );

    -- Signal Assignments
    ---------------------
    LOWER          <= PinSignal_U2_L; -- ObjectKind=Net|PrimaryId=LOWER[3..0]
    PARITY         <= PinSignal_U2_P; -- ObjectKind=Net|PrimaryId=NetU2_P
    PinSignal_U2_L <= LOWER; -- ObjectKind=Net|PrimaryId=LOWER[3..0]
    PinSignal_U2_U <= UPPER; -- ObjectKind=Net|PrimaryId=UPPER[3..0]
    UPPER          <= PinSignal_U2_U; -- ObjectKind=Net|PrimaryId=UPPER[3..0]

end structure;
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