📄 os_cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/OS-II
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2006,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; Generic ARM
Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V2.84
12 00000000 ; By : Jean J. Labrosse
13 00000000 ;
14 00000000 ; For : ARMv7M Cortex-M3
15 00000000 ; Mode : Thumb2
16 00000000 ; Toolchain : RealView Development Suite
17 00000000 ; RealView Microcontroller Development Kit (
MDK)
18 00000000 ; ARM Developer Suite (ADS)
19 00000000 ; Keil uVision
20 00000000 ;*******************************************************
*************************************************
21 00000000
22 00000000 EXTERN OSRunning ; External referenc
es
23 00000000 EXTERN OSPrioCur
24 00000000 EXTERN OSPrioHighRdy
25 00000000 EXTERN OSTCBCur
26 00000000 EXTERN OSTCBHighRdy
27 00000000 EXTERN OSIntNesting
28 00000000 EXTERN OSIntExit
29 00000000 EXTERN OSTaskSwHook
30 00000000
31 00000000
32 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
33 00000000 EXPORT OS_CPU_SR_Restore
34 00000000 EXPORT OSStartHighRdy
35 00000000 EXPORT OSCtxSw
36 00000000 EXPORT OSIntCtxSw
37 00000000 EXPORT OSPendSV
38 00000000
39 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; interrupt control
state register
40 00000000 E000ED20
NVIC_SYSPRI2
EQU 0xE000ED20 ; system priority r
egister (2)
41 00000000 00000000
NVIC_PENDSV_PRI
EQU 0x00000000 ; PendSV priority v
ARM Macro Assembler Page 2
alue (lowest)
42 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; value to trigger
PendSV exception
43 00000000
44 00000000
45 00000000 ;*******************************************************
**************************************************
46 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
47 00000000 ;
48 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
49 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
50 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
51 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
52 00000000 ; into the CPU's status register.
53 00000000 ;
54 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
55 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
56 00000000 ;
57 00000000 ;
58 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
59 00000000 ;
60 00000000 ; void Task (void *p_arg)
61 00000000 ; {
62 00000000 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
63 00000000 ; OS_CPU_SR cpu_sr;
64 00000000 ; #endif
65 00000000 ;
66 00000000 ; :
67 00000000 ; :
68 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
69 00000000 ; :
70 00000000 ; :
71 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
72 00000000 ; :
73 00000000 ; :
74 00000000 ; }
75 00000000 ;
76 00000000 ; 2) OS_CPU_SaveSR() is implemented as reco
mmended by Atmel's application note:
77 00000000 ;
78 00000000 ; (N/A for Cortex-M3) "Disabling Interrupt
s at Processor Level"
79 00000000 ;*******************************************************
**************************************************
80 00000000
81 00000000 AREA |.text|, CODE, READONLY, ALIGN=
2
ARM Macro Assembler Page 3
82 00000000 THUMB
83 00000000 REQUIRE8
84 00000000 PRESERVE8
85 00000000
86 00000000
87 00000000 OS_CPU_SR_Save
88 00000000 F3EF 8010 MRS R0, PRIMASK ; set prio int mask
to mask all (excep
t faults)
89 00000004 B672 CPSID I
90 00000006 4770 BX LR
91 00000008
92 00000008 OS_CPU_SR_Restore
93 00000008 F380 8810 MSR PRIMASK, R0
94 0000000C 4770 BX LR
95 0000000E
96 0000000E
97 0000000E ;*******************************************************
**************************************************
98 0000000E ; START MULTITA
SKING
99 0000000E ; void OSStartHigh
Rdy(void)
100 0000000E ;
101 0000000E ; This function uses the context switcher (see below) to
cause the first task to start.
102 0000000E ; This is because for Cortex-M3 it makes most sense to i
mplement a context switch within
103 0000000E ; an exception handler, to take advantage of the process
or's auto context save and restore
104 0000000E ; features.
105 0000000E ;
106 0000000E ; Note(s) : 1) OSStartHighRdy() MUST:
107 0000000E ; a) Setup PendSV exception priority to low
est,
108 0000000E ; b) Set initial psp to 0, to tell context
switcher this is first run
109 0000000E ; c) Set OSRunning to TRUE,
110 0000000E ; d) Trigger PendSV exception,
111 0000000E ; e) Enable interrupts (tasks will run with
ints enabled)
112 0000000E ;*******************************************************
**************************************************
113 0000000E
114 0000000E OSStartHighRdy
115 0000000E
116 0000000E 4C27 LDR R4, =NVIC_SYSPRI2 ; set the Pen
dSV exception prior
ity
117 00000010 F04F 0500 LDR R5, =NVIC_PENDSV_PRI
118 00000014 6025 STR R5, [R4]
119 00000016
120 00000016 F04F 0400 MOV R4, #0 ; set the PSP to 0
for initial context
switch call
121 0000001A F384 8809 MSR PSP, R4
122 0000001E
123 0000001E 4C20 LDR R4, __OS_Running
; OSRunning = TRUE
ARM Macro Assembler Page 4
124 00000020 F04F 0501 MOV R5, #1
125 00000024 7025 STRB R5, [R4]
126 00000026
127 00000026 4C22 LDR R4, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
128 00000028 F04F 5580 LDR R5, =NVIC_PENDSVSET
129 0000002C 6025 STR R5, [R4]
130 0000002E
131 0000002E B662 CPSIE I ; enable interrupts
at processor level
132 00000030 OSStartHang
133 00000030 E7FE B OSStartHang ; should never get
here
134 00000032
135 00000032
136 00000032 ;*******************************************************
**************************************************
137 00000032 ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
138 00000032 ;
139 00000032 ; Note(s) : 1) OSCtxSw() is called when OS wants to do a
task context switch
140 00000032 ; This function triggers the PendSV excepti
on which is where the
141 00000032 ; real work is done.
142 00000032 ;*******************************************************
**************************************************
143 00000032
144 00000032 OSCtxSw
145 00000032 4C1F LDR R4, =NVIC_INT_CTRL ; trigger th
e PendSV exception
(causes context swi
tch)
146 00000034 F04F 5580 LDR R5, =NVIC_PENDSVSET
147 00000038 6025 STR R5, [R4]
148 0000003A 4770 BX LR
149 0000003C
150 0000003C ;*******************************************************
**************************************************
151 0000003C ; PERFORM A CONTEXT SWITCH (From inter
rupt level) - OSIntCtxSw()
152 0000003C ;
153 0000003C ; Notes: 1) This function is called by OSIntExit() wh
en it determines a context
154 0000003C ; switch is needed as the result of an inte
rrupt.
155 0000003C ;
156 0000003C ; 2) This function simply triggers a PendSV ex
ception which will cause the
157 0000003C ; OSPendSV to run whenever there are no mor
e interrupts active
158 0000003C ; and interrupts are enabled.
159 0000003C ;*******************************************************
**************************************************
160 0000003C
161 0000003C OSIntCtxSw
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