reset.c

C语言编写的监控中心终端程序。基于GPRS上传收发数据功能

/*
** FILE
** reset.c
**
** DESCRIPTION
** provide system boot-up CPU invariant reset code.
**
** *NOTE* this file is split from sysmain.c
*/

#include "config.h"
#include "global.h"
#include "macro.h"
#include "regmap.h"
#include "dma.h"
#include "cddsp.h"
#include "mon.h"
#include "memmap.h"
#include "func.h"

#include "ir.h"

#include "cpu.h"
#include "intdef.h"

#include "reset.h"
#include "hwsetup.h"

extern int init_audio(void);

/*
** FUNCTION
** reset_system
**
** DESCRIPTION
** reset system to a known state
*/
#define	TASKS			14

static const UINT16 task_priority_table[TASKS] = {
    (RF_TASK_PR		<< 8	| 0x00),
    (RF_TASK_SR		<< 8	| 0x01),
    (RF_TASK_OR		<< 8	| 0x02),
    (RF_TASK_AUP	<< 8	| 0x03),
    (RF_TASK_MR		<< 8	| 0x05),
    (RF_TASK_MW		<< 8	| 0x06),
    (RF_TASK_VR		<< 8	| 0x07),
    (RF_TASK_CDAW	<< 8	| 0x04),
    (RF_TASK_RD		<< 8	| 0x08),
    (RF_TASK_DDIM24	<< 8	| 0x09),
    (RF_TASK_DDIM16	<< 8	| 0x0a),
    (RF_TASK_LBC	<< 8	| 0x0b),
    (RF_TASK_DPDM24	<< 8	| 0x0c),
    (RF_TASK_DPDM16	<< 8	| 0x0d),
};


/*
** FUNCTION
** reset_system()
**
** DESCRIPTION
**  1. setup register file pointer
**  2. reset modules
**  3. setup mmu state
**  4. setup rom wait states
*/
void reset_system()
{
    /*
     ** setup register file pointers
     */
    InitRegFile();

    regs0->emulation = 1;
    regs0->reset = 0;			// enable sub-systems
//  regs0->watchdog = 1;
    regs0->dis_tv_out = 1 << 3;		// kevinlu 2002/11/13 08:30PM
    regs0->gpio_sel_aux = 0xffff;	// kevinlu 2002.10.05 for start up green screen
    regs0->gpio_sel_aux = 0;
#ifdef SUPPORT_GPIO_BUS_FUNCTION
    regs0->gpio_sel_aux = 0x10;
#else
    regs0->gpio_sel_aux = 0x50;
#endif

    init_audio();

    /*
     ** setup register file items
     */
    config_memory(MEM_CONFIG_LORESN);

    /*
     ** setup MMU priority
     */

#if 1
/*
    regs0->ds_priority		= 1;
    regs0->cd_priority		= 2;
    regs0->ogt_priority		= 3;
    regs0->osd_priority		= 4;
    regs0->pcm_priority		= 5;
    regs0->mr_priority		= 6;
    regs0->mw_priority		= 7;
    regs0->vr_priority		= 8;
    regs0->aud_priority		= 9;
    regs0->rd_priority		= 10;
    regs0->rl_priority		= 11;
    regs0->x6502_priority	= 12;
*/

    regs0->ds_priority		= 2;
    regs0->cd_priority		= 1;
    regs0->ogt_priority		= 3;
    regs0->osd_priority		= 4;
    regs0->pcm_priority		= 5;
    regs0->aud_priority		= 6;
    regs0->mr_priority		= 8;
    regs0->mw_priority		= 9;
    regs0->vr_priority		= 10;
    regs0->rd_priority		= 11;
    regs0->rl_priority		= 12;
    regs0->x6502_priority	= 7;
#endif

    /*
     ** Setup ROM0 speed
     **
     ** *NOTE* ROM access time will be n+3 cycles.
     **
     **        108MHz  81MHz   67.5MHz 54MHz
     **    1 (4)   36.8    48  59.2    74
     **    2 (5)   46  60  74  92.5
     **    3 (6)   55.2    72  88.8    111
     **    4 (7)   64.4    84  103.6   129.5
     **    5 (8)   73.6    96  118.4   148
     **    6 (9)   82.8    108 133.2   166.5
     */
#ifdef SUPPORT_DISCMAN		// kevinlu 2002/10/6 12:17AM
    regs0->rom_config = (4 << 0) | (4 << 4) | (4 << 8) | (4 << 12);	// 7cycle: 84ns ROM
#else
#ifdef  SIMULATION_FAST
    regs0->rom_config = (1 << 0) | (1 << 4) | (1 << 8) | (1 << 12);	// 4cycle: ..
#else
    regs0->rom_config = (5 << 0) | (5 << 4) | (5 << 8) | (5 << 12);	// 7cycle: 84ns ROM
#endif
#endif
//  regs0->rom_config = 4;

    /*
     ** Set limit of video-decoding
     */
    regs0->video_decode_time = 0x01;

    /*
     ** setup SDRAM PAD delay
     */
#if CONFIG==CONFIG_COMBO_SVCD
//  regs0->sdram_config = 3;
#else
    regs0->edo_config = EDO_CONFIG;
#endif
}

/*
** FUNCTION
** reset_all
**
** DESCRIPTION
** reset all, including some interface.
*/
void reset_all(void)
{
#if 0		// kevinlu 2001.12.28
    UINT32		*p, i;

    p = (UINT32 *) 0x88000000;
    for(i = 0; i < 0x20000; i++) {
	*(p + i) = 0;
    }
#endif

    cpu_intr_disable(); 	// disable CPU-level intr_enable
//  kevinlu mark 2002/10/6 12:15AM because timming is bad for TV 27MHz
//  reset_system();		// reset system
    MacroAbort();

    /*
     ** reset DMA_push/DMA_pop functionality
     */
    dmabuf_ptr = 0;

#ifdef SUPPORT_EPP_DBG
#if SUPPORT_EPP
    reset_epp();
#endif
#endif

    /*
     ** reset TV system
     */
    vpp_zoom = 1;

    /*
     ** reset DSA hardware state
     */
    regs0->timer0_ctrl = TIMER_CONFIG_100ms;

    /*
     ** audio-clock
     */
    regs0->audio_clkgen = RF_AUDCLK_16934400;

    /*
     ** restart interrupt
     */
    regs0->intr_status = -1;            // reset intr_flag (clear-upon-write)
    regs0->intr_status = 0;

    /*
     ** watchdog setup
     */
    regs0->watchdog = 1;

    /* reset intr_mask */
#ifdef LINEAR_PLAYBACK
    regs0->intr_mask = INTR_UART | INTR_FIELD_END | INTR_PIC_END;
#else
//  charles 2002/4/22 for stop -> no logo problem
    regs0->intr_mask = /* INTR_TIMER0 | INTR_TIMER1 | */
		       INTR_UART | INTR_WATCHDOG | INTR_FIELD_END | INTR_PIC_END;
#endif

    cpu_set_intr_mask(0xff);		// enable CPU-level intr_mask
    cpu_intr_enable();  		// enable CPU-level intr_enable
}