📄 splxx.inc
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D_Timer_Source2_Mask: .EQU %00011000
D_Timer_Source2_LSCK: .EQU %00000000
D_Timer_Source2_LSCK_Timer: .EQU %00001000
D_Timer_Source2_EXT2: .EQU %00010000
D_Timer_Source2_VDD: .EQU %00011000
D_Timer_EXT2_CFG: .EQU %00000000
D_Timer_EXT2_Div2_CFG: .EQU %00100000
D_Timer_Falling_Count: .EQU %00000000
D_Timer_rising_Count: .EQU %01000000
D_Timer_Disable: .EQU %00000000
D_Timer_Enable: .EQU %10000000
;-------------------------------------------------------------------------------
P_0AH_TimerLow_Data: .EQU $0A
P_0BH_TimerHigh_Data: .EQU $0B
P_0CH_Timer_Source1: .EQU $0C
D_HSCK_Timer_Mask: .EQU %00000111
D_HSCK_Timer_37_9_16: .EQU %00000000
D_HSCK_Timer_37_9_8: .EQU %00000001
D_HSCK_Timer_37_9_4: .EQU %00000010
D_HSCK_Timer_37_9_2: .EQU %00000011
D_HSCK_Timer_37_9: .EQU %00000100
D_HSCK_Timer_HSCK_8: .EQU %00000101
D_HSCK_Timer_HSCK_4: .EQU %00000110
D_HSCK_Timer_HSCK_2: .EQU %00000111
D_HSCK_INT_Mask: .EQU %00011000
D_HSCK_INT_37_9_16: .EQU %00000000
D_HSCK_INT_37_9_8: .EQU %00001000
D_HSCK_INT_37_9_4: .EQU %00010000
D_HSCK_INT_37_9_2: .EQU %00011000
;-------------------------------------------------------------------------------
P_0DH_Timer_Source2: .EQU $0D
D_LSCK_Timer_Mask: .EQU %00000111
D_LSCK_Timer_4HZ: .EQU %00000000
D_LSCK_Timer_8HZ: .EQU %00000001
D_LSCK_Timer_16HZ: .EQU %00000010
D_LSCK_Timer_32HZ: .EQU %00000011
D_LSCK_Timer_64HZ: .EQU %00000100
D_LSCK_Timer_128HZ: .EQU %00000101
D_LSCK_Timer_1024HZ: .EQU %00000110
D_LSCK_Timer_4096HZ: .EQU %00000111
D_2Hz_1Hz_SEL: .EQU %00001000
D_LSCK_INT_Mask: .EQU %01110000
D_LSCK_INT_4HZ: .EQU %00000000
D_LSCK_INT_8HZ: .EQU %00010000
D_LSCK_INT_16HZ: .EQU %00100000
D_LSCK_INT_32HZ: .EQU %00110000
D_LSCK_INT_64HZ: .EQU %01000000
D_LSCK_INT_128HZ: .EQU %01010000
D_LSCK_INT_1024HZ: .EQU %01100000
D_LSCK_INT_4096HZ: .EQU %01110000
;-------------------------------------------------------------------------------
P_0EH_INT_SET: .EQU $0E
;***Set both inetrrupt source and wakeup source
D_INT_EXT1: .EQU %00000001
D_INT_EXT2: .EQU %00000010
D_INT_T2HZ: .EQU %00000100
D_INT_HSCK_N: .EQU %00001000
D_INT_LSCK_INT: .EQU %00010000
D_INT_TMO: .EQU %00100000
D_INT_KEYC: .EQU %01000000
D_INT_NMI: .EQU %10000000
;-------------------------------------------------------------------------------
P_0FH_System_CTL: .EQU $0F
D_Wait_1st_Byte: .EQU %00000001
D_Wait_Mode: .EQU %10001110
D_Normal_Mode: .EQU %00001110
D_HighSpeedCLK_1st_Byte: .EQU %00000010
D_HighSpeedCLK_Disable: .EQU %10001101
D_HighSpeedCLK_Enable: .EQU %00001101
D_LowSpeedCLK_1st_Byte: .EQU %00000011
D_LowSpeedCLK_Disable: .EQU %10001100
D_LowSpeedCLK_Enable: .EQU %00001100
D_WatchDog_Clr_1st_Byte: .EQU %00000100
D_WatchDog_Clr: .EQU %10001011
D_32K_Strong_Auto_1st_Byte: .EQU %00000101
D_32K_AutoMode: .EQU %00001010
D_32K_StrongMode: .EQU %10001010
D_WakeUp_Ctl_1st_Byte: .EQU %00000110
D_WakeUp_From_RESET: .EQU %00001001
D_WakeUp_From_NextInst: .EQU %10001001
;-------------------------------------------------------------------------------
P_10H_IO_Config: .EQU $10
D_PortB0_PullHigh: .EQU %00000001
D_PortB1_PullHigh: .EQU %00000010
D_PortB23_PullHigh: .EQU %00000100
D_PortBHigh_PullHigh: .EQU %00001000
D_PortB3_Segment30: .EQU %00010000
D_PortB4_Segment31: .EQU %00100000
D_PortA1_RisingEdge_INT: .EQU %01000000
D_PortA2_RisingEdge_INT: .EQU %10000000
;-------------------------------------------------------------------------------
P_11H_LCDCLK_CTL: .EQU $11
P_12H_RST_Flag: .EQU $12
D_Reset_Flag_Mask: .EQU %00011111
D_Power_On_Flag: .EQU %00000001
D_EXT_Reset_Flag: .EQU %00000010
D_WatchDog_Reset_Flag: .EQU %00000100
D_ErrorAddr_Reset_Flag: .EQU %00001000
D_LVR_Flag: .EQU %00010000
;-------------------------------------------------------------------------------
P_13H_RFC_CTL: .EQU $13
D_RFC_Disable: .EQU %00000000
D_RFC_Enable: .EQU %00000001
;-------------------------------------------------------------------------------
.ENDIF
.IFDEF SPL15Ax
.PAGE0
;-------------------------------------------------------------------------------
; I/O configuration for hardware system
;-------------------------------------------------------------------------------
P_00H_PortCD_Ctrl: EQU $0
PortCDInput: EQU 0
PortCD0Input: EQU 0
PortCD1Input: EQU 0
PortCD2Input: EQU 0
PortCD3Input: EQU 0
PortCDOutput: EQU %00001111
PortCD0Output: EQU %00000001
PortCD1Output: EQU %00000010
PortCD2Output: EQU %00000100
PortCD3Output: EQU %00001000
PortCDPureInput:EQU %01000000
PortCDPullDown: EQU %00000000
PortCDBufferOut:EQU %00000000
PortCDOpenDrain:EQU %01000000
P_04H_PortCD: EQU $4
;-------------------------------------------------------------------------------
; PortABPC (W) : b0 ---> AB Port low nibble I/O control
; Input : 1 : Pure Input
; 0 : Pull High/Low ----> data = 1 pull high , data = 0 pull low
; Output : 1 : open drain P
; 0 : normal
;
; b1 ---> AB Port high nibble I/O control
; Input : 1 : Pure Input
; 0 : Pull High/Low ----> data = 1 pull high , data = 0 pull low
; Output : 1 : open drain N
; 0 : normal
P_1EH_PortAB_Ctrl: EQU $1E
P_03H_PortAB: EQU $3
P_34H_PortAB_ConfigCtrl: EQU $34
P_05H_PortEF: EQU $5
P_06H_PortEF_Ctrl: EQU $06
P_35H_PortEFConfigCtrl: EQU $35
;-------------------------------------------------------------------------------
P_07H_ROMBankSel: EQU $7
DummyAreaLowAddr EQU 00H
DummyAreaHighAddr EQU 80H
DummyAreaBankAddr EQU 03H
DummySkipLowAddr EQU 00H
DummySkipHighAddr EQU 80H
DummySkipBankAddr EQU 03H
BankMask: EQU %00000111
;-------------------------------------------------------------------------------
; WakeUpCtrl: Sleeping Wake up control (R/W)
; (write 1 for option enable, Write 0 for option disable and also
; Clear the correspondence Hardware flag)
; (Read 1 when the wakeup event is take place)
; b0 : Wake Up when EF Port 8 key changed
; b1 : Wake Up when TimeBaseL 2Hz / 1Hz depend on P_0AH_TimeBaseCtrl(0A)
; b2 : Wake Up when timer 0 overflow
; b3 : Wake Up when TimeBaseH coming
; (TimeBaseH 4Hz, 8Hz, 16Hz, 32Hz depend on P_0AH_TimeBaseCtrl(0AH))
; b4..b7: reserved
;-------------------------------------------------------------------------------
P_08H_WakeUpCtrl: EQU $8
WakeUpPortEF: EQU %00000001
WakeUpTimeBaseL:EQU %00000010
WakeUp2Hz: EQU %00000010
WakeUpTimer0: EQU %00000100
WakeUpTimeBaseH:EQU %00001000
WakeUpMask: EQU %00000111
;-------------------------------------------------------------------------------
; Sleep : Write "0FH" to this port to start Sleeping (W)
;-------------------------------------------------------------------------------
P_09H_Sleep: EQU $9
;-------------------------------------------------------------------------------
; TimeBaseCtrl: Write to setup timebase
; b1,b0:
; 0 0 -> Setup TimeBaseH as 4Hz
; 0 1 -> Setup TimeBaseH as 8Hz
; 1 0 -> Setup TimeBaseH as 16Hz
; 1 1 -> Setup TimeBaseH as 32Hz
; b7: TimeBaseL as 2Hz(0)/1Hz(1)
;
; b7..b0: Read back as TimeBase counter value base on 64Hz
;
;-------------------------------------------------------------------------------
P_0AH_TimerXHz: EQU $A
TimeBaseH4Hz: EQU %00000000
TimeBaseH8Hz: EQU %00000001
TimeBaseH16Hz: EQU %00000010
TimeBaseH32Hz: EQU %00000011
TimeBaseL2Hz: EQU %00000000
TimeBaseL1Hz: EQU %10000000
;-------------------------------------------------------------------------------
; TimerCtrl: Counter/Timer0 clock source and Mode selection (W)
; b7 : Timer1,Timer0 Enable(1)/Disable(0)
; b6 : Timer1 Counts CLK32(1)/SystemClockR-Osc(0)
; b5 : Timer0 in Timer mode Counts Overflow of Timer1(1)/SystemClockR-Osc(0)
; b4 : Timer0 Counter mode(1)/ Timer mode(0)
; b3,b2: Timer0 Counter mode input #1 source select
; 0 0: PortCD.1
; 0 1: VDD
; 1 0: TimeBaseH
; 1 1: CLK128Hz
; b1,b0: Timer0 Counter mode input #2 source select
; 0 0: PortCD.0 (Ext. clock )
; 0 1: 455KHz ( X'tal )
; 1 0: SystemClockR-Osc
; 1 1: CLK32 ( X'tal )
;
; Note: SystemClockCPU = SystemClockR-Osc/2
; CLK32,CLK128,TimeBaseH,TimeBaseL are generated by crystal 32768Hz
;
;-------------------------------------------------------------------------------
P_0BH_TimerModeCtrl: EQU 0BH
TimerEnable: EQU %10000000
TimerDisable: EQU %00000000
Tm1CountCLK32: EQU %01000000
Tm1CountROsc: EQU %00000000
Tm0CountTm1: EQU %00100000
Tm0CountROsc: EQU %00000000
Tm0CounterMode: EQU %00010000
Tm0TimerMode: EQU %00000000
Tm0Src1AsCDB1: EQU %00000000
Tm0Src1AsVDD: EQU %00000100
Tm0Src1AsTimeBaseH: EQU %00001000
Tm0Src1AsCLK128: EQU %00001100
Tm0Src2AsCDB0: EQU %00000000
Tm0Src2As455K: EQU %00000001
Tm0Src2AsROsc: EQU %00000010
Tm0Src2AsCLK32: EQU %00000011
;-------------------------------------------------------------------------------
; C32K : Crystal Oscillator Control (W)
; b5 : Normal mode(0)/Test mode(1)
; b7 : Enable(0)/Disable(1)
;-------------------------------------------------------------------------------
P_0CH_32OSC_Ctrl: EQU 0CH
OSC32KTest: EQU %00100000
OSC32KWeak: EQU %01000000
OSC32KStrong: EQU %00000000
OSC32KDisable: EQU %10000000
OSC32KEnable: EQU %00000000
;-------------------------------------------------------------------------------
; Ints : interrupt control register (R/W), write 0 to this register will make
; the correspondence interrupt disable, and also clear interrupt harware
; flag.
; (R) for flags of correspondence interrupt is generated.
; b0 : External interrupt source (PortCD.b1 <falling edge>)
; b1 : CLK2K (32768 / 16)
; b2 : CLK128 (32768 / 256)
; b3 : TimeBaseL -> 2Hz/1Hz depend on P_0AH_TimeBaseCtrl
; b4 : TimeBaseH -> 4Hz/8Hz/16Hz/32Hz depend on P_0AH_TimeBaseCtrl
; d5 : Timer1 interrupt enable (can define as IRQ or NMI by bit7)
; d6 : Timer0 interrupt enable (only IRQ can be configurated)
; d7 : 0 -> Timer1 interrupt as NMI
; 1 -> Timer1 interrupt as IRQ
;-------------------------------------------------------------------------------
P_0DH_Ints: EQU $0d
ExtIntEnable: EQU %00000001
CLK2KIntEnable: EQU %00000010
D_CLK2K: EQU %00000010
CLK128IntEnable: EQU %00000100
D_CLK128: EQU %00000100
TimeBaseLIntEnable: EQU %00001000
T2HzIntEnable EQU TimeBaseLIntEnable
TimeBaseHIntEnable: EQU %00010000
TimerXEnable: EQU %00010000
Timer1IntEnable: EQU %00100000
Timer0IntEnable: EQU %01000000
D_TimerCh0: EQU Timer1IntEnable
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