📄 splxx.inc
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LCD_Latch: EQU %00000000
LCD_TimerCounterPWM: EQU %00001000
LCD_AutoLoadCOM: EQU %00010000
LCD_OnlyCOM0: EQU %00000000
LCD_1_2_Bias: EQU %00000000
LCD_1_3_Bias: EQU %00100000
LCD_4Duty: EQU %00000000
LCD_3Duty: EQU %10000000
LCD_2Duty: EQU %11000000
.ENDIF
.IFDEF SPL11Ax
.PAGE0
;-------------------------------------------------------------------------------
; I/O configuration for hardware system
;-------------------------------------------------------------------------------
P_00H_PortA_Data: .EQU $00
P_01H_PortA_Dir: .EQU $01
P_02H_PortA_Attrib: .EQU $02
P_03H_PortB_Data: .EQU $03
P_04H_LCD_CTL: .EQU $04
D_Duty_Mask: .EQU %00000111
D_1_3_Duty: .EQU %00000000
D_1_4_Duty: .EQU %00000001
D_1_5_Duty: .EQU %00000010
D_1_8_Duty: .EQU %00000011
D_1_9_Duty: .EQU %00000100
D_1_10_Duty: .EQU %00000101
D_1_11_Duty: .EQU %00000110
D_1_12_Duty: .EQU %00000111
D_Bias_Mask: .EQU %00011000
D_1_2_Bias: .EQU %00000000
D_1_3_Bias: .EQU %00001000
D_1_4_Bias: .EQU %00010000
D_LCD_Mask: .EQU %01100000
D_LCD_Off: .EQU %00000000
D_LCD_Normal: .EQU %00100000
D_Dots_On: .EQU %01000000
D_Dots_Off: .EQU %01100000
D_Pump_CLK_8K: .EQU %00000000
D_Pump_CLK_32K: .EQU %10000000
;-------------------------------------------------------------------------------
P_05H_CPU_CLK: .EQU $05
D_CPU_CLK_Mask: .EQU %00000111
D_CPU_CLK_HSCK_16: .EQU %00000000
D_CPU_CLK_HSCK_8: .EQU %00000001
D_CPU_CLK_HSCK_4: .EQU %00000010
D_CPU_CLK_HSCK_2: .EQU %00000011
D_CPU_CLK_LSCK: .EQU %00000100
;-------------------------------------------------------------------------------
P_06H_IR_Duty_CTL: .EQU $06
D_IR_Pulse_Duty_Mask: .EQU %00000111
D_IR_Pulse_Duty_0_8: .EQU %00000000
D_IR_Pulse_Duty_1_8: .EQU %00000001
D_IR_Pulse_Duty_2_8: .EQU %00000010
D_IR_Pulse_Duty_3_8: .EQU %00000011
D_IR_Pulse_Duty_4_8: .EQU %00000100
D_IR_Pulse_Duty_5_8: .EQU %00000101
D_IR_Pulse_Duty_6_8: .EQU %00000110
D_IR_Pulse_Duty_7_8: .EQU %00000111
D_IR_SW_CTL: .EQU %00000000
D_IR_TMO_CTL: .EQU %00001000
D_IR_Off: .EQU %00000000
D_IR_On: .EQU %00010000
;-------------------------------------------------------------------------------
P_07H_WKU_Set: .EQU $07
D_WKU_EXT1: .EQU %00000001
D_WKU_EXT2: .EQU %00000010
D_WKU_T2HZ: .EQU %00000100
D_WKU_HSCK_N: .EQU %00001000
D_WKU_LSCK_INT: .EQU %00010000
D_WKU_TMO: .EQU %00100000
D_WKU_KEYC: .EQU %01000000
D_TMO_NMI: .EQU %10000000
;-------------------------------------------------------------------------------
P_08H_WKU_CLR: .EQU $08
P_09H_Timer_Set: .EQU $09
D_Timer_Source1_Mask: .EQU %00000011
D_Timer_Source1_HSCK: .EQU %00000000
D_Timer_Source1_HSCK_Timer: .EQU %00000001
D_Timer_Source1_EXT1: .EQU %00000010
D_Timer_Source1_VDD: .EQU %00000011
D_Timer_Source1_EXT2: .EQU %00000100
D_Timer_Source2_Mask: .EQU %00011000
D_Timer_Source2_LSCK: .EQU %00000000
D_Timer_Source2_LSCK_Timer: .EQU %00001000
D_Timer_Source2_EXT2: .EQU %00010000
D_Timer_Source2_VDD: .EQU %00011000
D_Timer_EXT2_CFG: .EQU %00000000
D_Timer_EXT2_Div2_CFG: .EQU %00100000
D_Timer_Falling_Count: .EQU %00000000
D_Timer_rising_Count: .EQU %01000000
D_Timer_Disable: .EQU %00000000
D_Timer_Enable: .EQU %10000000
P_0AH_TimerLow_Data: .EQU $0A
P_0BH_TimerHigh_Data: .EQU $0B
P_0CH_Timer_Source1: .EQU $0C
D_HSCK_Timer_Mask: .EQU %00000111
D_HSCK_Timer_37_9_16: .EQU %00000000
D_HSCK_Timer_37_9_8: .EQU %00000001
D_HSCK_Timer_37_9_4: .EQU %00000010
D_HSCK_Timer_37_9_2: .EQU %00000011
D_HSCK_Timer_37_9: .EQU %00000100
D_HSCK_Timer_HSCK_8: .EQU %00000101
D_HSCK_Timer_HSCK_4: .EQU %00000110
D_HSCK_Timer_HSCK_2: .EQU %00000111
D_HSCK_INT_Mask: .EQU %00011000
D_HSCK_INT_37_9_16: .EQU %00000000
D_HSCK_INT_37_9_8: .EQU %00001000
D_HSCK_INT_37_9_4: .EQU %00010000
D_HSCK_INT_37_9_2: .EQU %00011000
;-------------------------------------------------------------------------------
P_0DH_Timer_Source2: .EQU $0D
D_LSCK_Timer_Mask: .EQU %00000111
D_LSCK_Timer_4HZ: .EQU %00000000
D_LSCK_Timer_8HZ: .EQU %00000001
D_LSCK_Timer_16HZ: .EQU %00000010
D_LSCK_Timer_32HZ: .EQU %00000011
D_LSCK_Timer_64HZ: .EQU %00000100
D_LSCK_Timer_128HZ: .EQU %00000101
D_LSCK_Timer_1024HZ: .EQU %00000110
D_LSCK_Timer_4096HZ: .EQU %00000111
D_2Hz_1Hz_SEL: .EQU %00001000
D_LSCK_INT_Mask: .EQU %01110000
D_LSCK_INT_4HZ: .EQU %00000000
D_LSCK_INT_8HZ: .EQU %00010000
D_LSCK_INT_16HZ: .EQU %00100000
D_LSCK_INT_32HZ: .EQU %00110000
D_LSCK_INT_64HZ: .EQU %01000000
D_LSCK_INT_128HZ: .EQU %01010000
D_LSCK_INT_1024HZ: .EQU %01100000
D_LSCK_INT_4096HZ: .EQU %01110000
;-------------------------------------------------------------------------------
P_0EH_INT_SET: .EQU $0E
;***Set both inetrrupt source and wakeup source
D_INT_EXT1: .EQU %00000001
D_INT_EXT2: .EQU %00000010
D_INT_T2HZ: .EQU %00000100
D_INT_HSCK_N: .EQU %00001000
D_INT_LSCK_INT: .EQU %00010000
D_INT_TMO: .EQU %00100000
D_INT_KEYC: .EQU %01000000
D_INT_NMI: .EQU %10000000
;-------------------------------------------------------------------------------
P_0FH_System_CTL: .EQU $0F
D_Wait_1st_Byte: .EQU %00000001
D_Wait_Mode: .EQU %10001110
D_Normal_Mode: .EQU %00001110
D_HighSpeedCLK_1st_Byte: .EQU %00000010
D_HighSpeedCLK_Disable: .EQU %10001101
D_HighSpeedCLK_Enable: .EQU %00001101
D_LowSpeedCLK_1st_Byte: .EQU %00000011
D_LowSpeedCLK_Disable: .EQU %10001100
D_LowSpeedCLK_Enable: .EQU %00001100
D_WatchDog_Clr_1st_Byte: .EQU %00000100
D_WatchDog_Clr: .EQU %10001011
D_32K_Strong_Auto_1st_Byte: .EQU %00000101
D_32K_AutoMode: .EQU %00001010
D_32K_StrongMode: .EQU %10001010
D_WakeUp_Ctl_1st_Byte: .EQU %00000110
D_WakeUp_From_RESET: .EQU %00001001
D_WakeUp_From_NextInst: .EQU %10001001
;-------------------------------------------------------------------------------
P_10H_IO_Config: .EQU $10
D_PortB0_PullHigh: .EQU %00000001
D_PortB1_PullHigh: .EQU %00000010
D_PortB23_PullHigh: .EQU %00000100
D_PortBHigh_PullHigh: .EQU %00001000
D_PortB3_Segment30: .EQU %00010000
D_PortB4_Segment31: .EQU %00100000
D_PortA1_RisingEdge_INT: .EQU %01000000
D_PortA2_RisingEdge_INT: .EQU %10000000
;-------------------------------------------------------------------------------
P_11H_LCDCLK_CTL: .EQU $11
P_12H_RST_Flag: .EQU $12
D_Reset_Flag_Mask: .EQU %00011111
D_Power_On_Flag: .EQU %00000001
D_EXT_Reset_Flag: .EQU %00000010
D_WatchDog_Reset_Flag: .EQU %00000100
D_ErrorAddr_Reset_Flag: .EQU %00001000
D_LVR_Flag: .EQU %00010000
;-------------------------------------------------------------------------------
P_13H_RFC_CTL: .EQU $13
D_RFC_Disable: .EQU %00000000
D_RFC_Enable: .EQU %00000001
.ENDIF
.IFDEF SPL12Ax
.PAGE0
;-------------------------------------------------------------------------------
; I/O configuration for hardware system
;-------------------------------------------------------------------------------
P_00H_PortA_Data: .EQU $00
P_01H_PortA_Dir: .EQU $01
P_02H_PortA_Attrib: .EQU $02
P_03H_PortB_Data: .EQU $03
P_04H_LCD_CTL: .EQU $04
D_Duty_Mask: .EQU %00000111
D_1_3_Duty: .EQU %00000000
D_1_4_Duty: .EQU %00000001
D_1_5_Duty: .EQU %00000010
D_1_8_Duty: .EQU %00000011
D_1_9_Duty: .EQU %00000100
D_1_10_Duty: .EQU %00000101
D_1_11_Duty: .EQU %00000110
D_1_12_Duty: .EQU %00000111
D_Bias_Mask: .EQU %00011000
D_1_2_Bias: .EQU %00000000
D_1_3_Bias: .EQU %00001000
D_1_4_Bias: .EQU %00010000
D_LCD_Mask: .EQU %01100000
D_LCD_Off: .EQU %00000000
D_LCD_Normal: .EQU %00100000
D_Dots_On: .EQU %01000000
D_Dots_Off: .EQU %01100000
D_Pump_CLK_8K: .EQU %00000000
D_Pump_CLK_32K: .EQU %10000000
;-------------------------------------------------------------------------------
P_05H_CPU_CLK: .EQU $05
D_CPU_CLK_Mask: .EQU %00000111
D_CPU_CLK_HSCK_16: .EQU %00000000
D_CPU_CLK_HSCK_8: .EQU %00000001
D_CPU_CLK_HSCK_4: .EQU %00000010
D_CPU_CLK_HSCK_2: .EQU %00000011
D_CPU_CLK_LSCK: .EQU %00000100
;-------------------------------------------------------------------------------
P_06H_IR_Duty_CTL: .EQU $06
D_IR_Pulse_Duty_Mask: .EQU %00000111
D_IR_Pulse_Duty_0_8: .EQU %00000000
D_IR_Pulse_Duty_1_8: .EQU %00000001
D_IR_Pulse_Duty_2_8: .EQU %00000010
D_IR_Pulse_Duty_3_8: .EQU %00000011
D_IR_Pulse_Duty_4_8: .EQU %00000100
D_IR_Pulse_Duty_5_8: .EQU %00000101
D_IR_Pulse_Duty_6_8: .EQU %00000110
D_IR_Pulse_Duty_7_8: .EQU %00000111
D_IR_SW_CTL: .EQU %00000000
D_IR_TMO_CTL: .EQU %00001000
D_IR_Off: .EQU %00000000
D_IR_On: .EQU %00010000
;-------------------------------------------------------------------------------
P_07H_WKU_Set: .EQU $07
D_WKU_EXT1: .EQU %00000001
D_WKU_EXT2: .EQU %00000010
D_WKU_T2HZ: .EQU %00000100
D_WKU_HSCK_N: .EQU %00001000
D_WKU_LSCK_INT: .EQU %00010000
D_WKU_TMO: .EQU %00100000
D_WKU_KEYC: .EQU %01000000
D_TMO_NMI: .EQU %10000000
;-------------------------------------------------------------------------------
P_08H_WKU_CLR: .EQU $08
P_09H_Timer_Set: .EQU $09
D_Timer_Source1_Mask: .EQU %00000011
D_Timer_Source1_HSCK: .EQU %00000000
D_Timer_Source1_HSCK_Timer: .EQU %00000001
D_Timer_Source1_EXT1: .EQU %00000010
D_Timer_Source1_VDD: .EQU %00000011
D_Timer_Source1_EXT2: .EQU %00000100
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