sv_iface.vhd

国外开源的一个片上网络系统的源代码

----------------------------------------------------------
--							--
--	SV_IFACE.vhd - Spartan to Virtex Interface	--
--	Copyright Nallatech Ltd. 1999			--
--	Description:					--
--	This module can be placed within the Virtex	--
--	on the Ballynuey card.  It's purpose is to	--
--	provide an easy interface to the Spartan on	--
--	the Ballynuey.					--
--	The design is split into two main parts.	--
--	These are the main interface control and the	--
--	DMA control.					--
--							--
----------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity SV_IFACE is
    generic (-- Number of memory blocks in memory map in bit size.
    		NUM_BLOCKSg : integer range 1 to 29;-- := 4;
    		-- Block size.
    		BLOCK_SIZEg : integer range 1 to 29;--:= 8;
    		-- Number of registers.
    		NUM_REGSg : integer range 1 to 29-- := 4
    		);	   
    port (
    	-- Interface clock.
        CLK: in STD_LOGIC;
        -- Global reset.
        RSTl: in STD_LOGIC;
        -- Indicates whether Spartan can receive data.
        BUSY: in STD_LOGIC;
        -- Indicates whether Spartan has data to send.
        EMPTY: in STD_LOGIC;
        -- Indicates that ADIO is address or data.
        AS_DSl: in STD_LOGIC;
        -- DMA engine is writing data out.
        DMA_WEN: in STD_LOGIC;
        -- DMA engine is reading data in.
        DMA_REN: in STD_LOGIC;
        -- Interrupt.
        INT: in STD_LOGIC;
        -- Read/Write enable.
        RENl_WENl: out STD_LOGIC;
        -- Indicates if Spartan is being read or being written to.
        RDl_WR: out STD_LOGIC;
        -- Interrupt to Spartan.
        INTl: out STD_LOGIC;
        -- Current active address.
        ADDRESS: out STD_LOGIC_VECTOR (30 downto 0);
        -- Write data into register.
        WRITE_STROBE: out STD_LOGIC;
        -- Read data from register.
        READ_STROBE: out STD_LOGIC;
        -- Current DMA count.
        COUNT: out STD_LOGIC_VECTOR (31 downto 0);
        -- Enable DMA engine.
        DMA_ENABLE: out STD_LOGIC;
        -- DMA direction.
        DMA_DIRECTION: out STD_LOGIC;
        -- DMA select.
        DMA_SEL: out STD_LOGIC_VECTOR (3 downto 0);
        -- DMA control is ready for DMA engine to send data.
        DMA_RDY: out STD_LOGIC;
        -- DMA control has data for DMA engin to read.
        DMA_DATA_AVAILABLE: out STD_LOGIC;
        -- Reset to rest of Virtex.
        RST: out STD_LOGIC;
        -- Synchronous reset.
        SYNC_RESET: out STD_LOGIC;
        -- DMA is reset.
        DMA_RESET: out STD_LOGIC;
        -- Data IO between Spartan and Virtex.
        ADIO: inout STD_LOGIC_VECTOR (31 downto 0);
        -- Internal data bus.
        DATA: inout STD_LOGIC_VECTOR (31 downto 0);
        -- Internal DMA data bus.
        DMA_DATA: inout STD_LOGIC_VECTOR (31 downto 0)
    );
end SV_IFACE;

architecture SV_IFACE_arch of SV_IFACE is

component IF_MAIN generic (	-- Number of memory blocks in memory map in bit size.
    				NUM_BLOCKSg : integer range 1 to 29;-- := 4;
    				-- Block size.
    				BLOCK_SIZEg : integer range 1 to 29;--:= 16;
    				-- Number of registers.
    				NUM_REGSg : integer range 1 to 29-- := 4
    				);
    			port (	-- Spartan - Virtex clock.
        			CLK: in STD_LOGIC;
        			-- Global reset.
        			RST: in STD_LOGIC;
        			-- Synchronous reset.
        			SYNC_RST: in STD_LOGIC;
        			-- Indicates if Spartan can receive data.
        			BUSY: in STD_LOGIC;
        			-- Indicates if Spartan has data to send.
        			EMPTY: in STD_LOGIC;
        			-- Address Strobe / Data Strobe.
        			AS_DSl: in STD_LOGIC;
        			-- DMA engine is writing to Spartan.
        			DMA_IN_FULL: in STD_LOGIC;
        			DMA_IN_EMPTY: in STD_LOGIC;
        			DMA_OUT_FULL: in STD_LOGIC;
        			-- DMA engine is reading from Spartan.
        			DMA_OUT_EMPTY: in STD_LOGIC;
        			-- Terminal count of DMA counter.
        			TERM_CNT: in STD_LOGIC;
        			-- DMA count output.
        			COUNT_OUT: in STD_LOGIC_VECTOR (31 downto 0);
        			-- DMA output.
        			DMA_OUT: in STD_LOGIC_VECTOR (31 downto 0);
        			-- Read Enable / Write Enable.
       	 			RENl_WENl: out STD_LOGIC;
        			-- Read / Write.
        			RDl_WR: out STD_LOGIC;
        			-- Load DMA count.
        			WR_COUNT: out STD_LOGIC;
        			-- Enable DMA engine.
        			DMA_ENABLE: out STD_LOGIC;
        			-- DMA direction.
        			DMA_DIRECTION: out STD_LOGIC;
        			-- DMA select.
        			DMA_SEL: out STD_LOGIC_VECTOR (3 downto 0);	 
					-- DMA Reset.
					DMA_RST: out STD_LOGIC;
        			-- Active address.
        			ADDRESS: out STD_LOGIC_VECTOR (30 downto 0);
       	 			-- Write to active register.
        			WR_STROBE: out STD_LOGIC;
        			-- Read from active register.
        			RD_STROBE: out STD_LOGIC;
        			-- Write DMA.
        			WR_DMA: out STD_LOGIC;
        			-- Read DMA.
        			RD_DMA: out STD_LOGIC;
        			-- DMA count input.
        			COUNT_IN: out STD_LOGIC_VECTOR (31 downto 0);
        			-- DMA input.
        			DMA_IN: out STD_LOGIC_VECTOR (31 downto 0);
        			-- Data to and from Spartan.
        			ADIO: inout STD_LOGIC_VECTOR (31 downto 0);
        			-- Data to and from user's design.
        			DATA: inout STD_LOGIC_VECTOR (31 downto 0)
    				);
end component;


-- Reset
signal RSTi : std_logic;

-- Synchronous reset.
signal SYNC_RSTi, SYNC_RSTid1 : std_logic;
signal SYNC_RSTid2 : std_logic;

-- DMA local FIFO signals.
signal DMA_IN_FULL : std_logic;
signal DMA_IN_EMPTY : std_logic;
signal DMA_OUT_FULL : std_logic;
signal DMA_OUT_EMPTY : std_logic;

-- Terminal count of DMA counter.
signal TERM_CNT : std_logic;

-- DMA count.
signal WR_COUNT : std_logic;
signal COUNT_OUT : std_logic_vector (31 downto 0);
signal COUNT_IN : std_logic_vector (31 downto 0);

-- DMA data.
signal RD_DMA : std_logic;
signal WR_DMA : std_logic;
signal DMA_OUT : std_logic_vector (31 downto 0);
signal DMA_IN : std_logic_vector (31 downto 0);

-- DMA direction signal and enable.
signal DMA_DIRECTIONi : std_logic;
signal DMA_ENABLEi : std_logic;
signal DMA_RSTi : std_logic;

signal BUSYd1 : std_logic;

begin

RSTi <= not RSTl;
RST <= RSTi;

-- Generate synchronous version of reset.
process (RSTi, CLK)
begin
	if RSTi='1' then
		SYNC_RSTi <= '1';
		SYNC_RSTid1 <= '1';
		SYNC_RSTid2 <= '1';
	elsif CLK'event and CLK='1' then	
		SYNC_RSTi <= '0';
		SYNC_RSTid1 <= SYNC_RSTi;
		SYNC_RSTid2 <= SYNC_RSTid1;
	end if;
end process;		

SYNC_RESET <= SYNC_RSTid2;

process (RSTi, CLK)
begin
	if RSTi='1' then
		BUSYd1 <= '1';
	elsif CLK'event and CLK='1' then
		BUSYd1 <= BUSY;
	end if;
end process;			

INTl <= not INT;

-- Main interface control.
H1_MAIN_CTRL : IF_MAIN generic map (	NUM_BLOCKSg => NUM_BLOCKSg,
    					BLOCK_SIZEg => BLOCK_SIZEg,
    					NUM_REGSg => NUM_REGSg
    					)
    			port map (	CLK => CLK,
        				RST => RSTi,
        				SYNC_RST => SYNC_RSTid2,
        				BUSY => BUSY,
        				EMPTY => EMPTY,
        				AS_DSl => AS_DSl,
        				DMA_IN_FULL => DMA_IN_FULL,
        				DMA_IN_EMPTY => DMA_IN_EMPTY,
        				DMA_OUT_FULL => DMA_OUT_FULL,
        				DMA_OUT_EMPTY => DMA_OUT_EMPTY,
        				TERM_CNT => TERM_CNT,
        				COUNT_OUT => COUNT_OUT,
        				DMA_OUT => DMA_OUT,
        				RENl_WENl => RENl_WENl,
        				RDl_WR => RDl_WR,
        				WR_COUNT => WR_COUNT,
        				DMA_ENABLE => DMA_ENABLEi,
        				DMA_DIRECTION => DMA_DIRECTIONi,
        				DMA_SEL => DMA_SEL,		
						DMA_RST => DMA_RSTi,
        				ADDRESS => ADDRESS,
       	 				WR_STROBE => WRITE_STROBE,
        				RD_STROBE => READ_STROBE,
        				WR_DMA => WR_DMA,
        				RD_DMA => RD_DMA,
        				COUNT_IN => COUNT_IN,
        				DMA_IN => DMA_IN,
        				ADIO => ADIO,
        				DATA => DATA
    					);
    				
end SV_IFACE_arch;