_network8x8.cpp.bak

国外开源的一个片上网络系统的源代码

	sc_signal<bool> dp_x1y4_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y4_xDO;
	sc_signal< sc_uint<32> > dp_x1y4_xADDR;
	sc_signal< bool > dp_x1y4_xCLK, dp_x1y4_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y5_ramADDR;
	sc_signal<sc_int<32> > dp_x1y5_ramDI;
	sc_signal<sc_int<32> > dp_x1y5_ramDO;
	sc_signal<bool> dp_x1y5_ramEN;
	sc_signal<bool> dp_x1y5_ramCLK;
	sc_signal<bool> dp_x1y5_ramWE;
	sc_signal<bool> dp_x1y5_ramRST;
	sc_signal<sc_uint<32> > dp_x1y5_romADDR;
	sc_signal<sc_int<32> > dp_x1y5_romDI;
	sc_signal<sc_int<32> > dp_x1y5_romDO;
	sc_signal<bool> dp_x1y5_romEN;
	sc_signal<bool> dp_x1y5_romCLK;
	sc_signal<bool> dp_x1y5_romWE;
	sc_signal<bool> dp_x1y5_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y5_xDO;
	sc_signal< sc_uint<32> > dp_x1y5_xADDR;
	sc_signal< bool > dp_x1y5_xCLK, dp_x1y5_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y6_ramADDR;
	sc_signal<sc_int<32> > dp_x1y6_ramDI;
	sc_signal<sc_int<32> > dp_x1y6_ramDO;
	sc_signal<bool> dp_x1y6_ramEN;
	sc_signal<bool> dp_x1y6_ramCLK;
	sc_signal<bool> dp_x1y6_ramWE;
	sc_signal<bool> dp_x1y6_ramRST;
	sc_signal<sc_uint<32> > dp_x1y6_romADDR;
	sc_signal<sc_int<32> > dp_x1y6_romDI;
	sc_signal<sc_int<32> > dp_x1y6_romDO;
	sc_signal<bool> dp_x1y6_romEN;
	sc_signal<bool> dp_x1y6_romCLK;
	sc_signal<bool> dp_x1y6_romWE;
	sc_signal<bool> dp_x1y6_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y6_xDO;
	sc_signal< sc_uint<32> > dp_x1y6_xADDR;
	sc_signal< bool > dp_x1y6_xCLK, dp_x1y6_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y7_ramADDR;
	sc_signal<sc_int<32> > dp_x1y7_ramDI;
	sc_signal<sc_int<32> > dp_x1y7_ramDO;
	sc_signal<bool> dp_x1y7_ramEN;
	sc_signal<bool> dp_x1y7_ramCLK;
	sc_signal<bool> dp_x1y7_ramWE;
	sc_signal<bool> dp_x1y7_ramRST;
	sc_signal<sc_uint<32> > dp_x1y7_romADDR;
	sc_signal<sc_int<32> > dp_x1y7_romDI;
	sc_signal<sc_int<32> > dp_x1y7_romDO;
	sc_signal<bool> dp_x1y7_romEN;
	sc_signal<bool> dp_x1y7_romCLK;
	sc_signal<bool> dp_x1y7_romWE;
	sc_signal<bool> dp_x1y7_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y7_xDO;
	sc_signal< sc_uint<32> > dp_x1y7_xADDR;
	sc_signal< bool > dp_x1y7_xCLK, dp_x1y7_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y0_ramADDR;
	sc_signal<sc_int<32> > dp_x2y0_ramDI;
	sc_signal<sc_int<32> > dp_x2y0_ramDO;
	sc_signal<bool> dp_x2y0_ramEN;
	sc_signal<bool> dp_x2y0_ramCLK;
	sc_signal<bool> dp_x2y0_ramWE;
	sc_signal<bool> dp_x2y0_ramRST;
	sc_signal<sc_uint<32> > dp_x2y0_romADDR;
	sc_signal<sc_int<32> > dp_x2y0_romDI;
	sc_signal<sc_int<32> > dp_x2y0_romDO;
	sc_signal<bool> dp_x2y0_romEN;
	sc_signal<bool> dp_x2y0_romCLK;
	sc_signal<bool> dp_x2y0_romWE;
	sc_signal<bool> dp_x2y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y0_xDO;
	sc_signal< sc_uint<32> > dp_x2y0_xADDR;
	sc_signal< bool > dp_x2y0_xCLK, dp_x2y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y1_ramADDR;
	sc_signal<sc_int<32> > dp_x2y1_ramDI;
	sc_signal<sc_int<32> > dp_x2y1_ramDO;
	sc_signal<bool> dp_x2y1_ramEN;
	sc_signal<bool> dp_x2y1_ramCLK;
	sc_signal<bool> dp_x2y1_ramWE;
	sc_signal<bool> dp_x2y1_ramRST;
	sc_signal<sc_uint<32> > dp_x2y1_romADDR;
	sc_signal<sc_int<32> > dp_x2y1_romDI;
	sc_signal<sc_int<32> > dp_x2y1_romDO;
	sc_signal<bool> dp_x2y1_romEN;
	sc_signal<bool> dp_x2y1_romCLK;
	sc_signal<bool> dp_x2y1_romWE;
	sc_signal<bool> dp_x2y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y1_xDO;
	sc_signal< sc_uint<32> > dp_x2y1_xADDR;
	sc_signal< bool > dp_x2y1_xCLK, dp_x2y1_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y2_ramADDR;
	sc_signal<sc_int<32> > dp_x2y2_ramDI;
	sc_signal<sc_int<32> > dp_x2y2_ramDO;
	sc_signal<bool> dp_x2y2_ramEN;
	sc_signal<bool> dp_x2y2_ramCLK;
	sc_signal<bool> dp_x2y2_ramWE;
	sc_signal<bool> dp_x2y2_ramRST;
	sc_signal<sc_uint<32> > dp_x2y2_romADDR;
	sc_signal<sc_int<32> > dp_x2y2_romDI;
	sc_signal<sc_int<32> > dp_x2y2_romDO;
	sc_signal<bool> dp_x2y2_romEN;
	sc_signal<bool> dp_x2y2_romCLK;
	sc_signal<bool> dp_x2y2_romWE;
	sc_signal<bool> dp_x2y2_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y2_xDO;
	sc_signal< sc_uint<32> > dp_x2y2_xADDR;
	sc_signal< bool > dp_x2y2_xCLK, dp_x2y2_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y3_ramADDR;
	sc_signal<sc_int<32> > dp_x2y3_ramDI;
	sc_signal<sc_int<32> > dp_x2y3_ramDO;
	sc_signal<bool> dp_x2y3_ramEN;
	sc_signal<bool> dp_x2y3_ramCLK;
	sc_signal<bool> dp_x2y3_ramWE;
	sc_signal<bool> dp_x2y3_ramRST;
	sc_signal<sc_uint<32> > dp_x2y3_romADDR;
	sc_signal<sc_int<32> > dp_x2y3_romDI;
	sc_signal<sc_int<32> > dp_x2y3_romDO;
	sc_signal<bool> dp_x2y3_romEN;
	sc_signal<bool> dp_x2y3_romCLK;
	sc_signal<bool> dp_x2y3_romWE;
	sc_signal<bool> dp_x2y3_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y3_xDO;
	sc_signal< sc_uint<32> > dp_x2y3_xADDR;
	sc_signal< bool > dp_x2y3_xCLK, dp_x2y3_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y4_ramADDR;
	sc_signal<sc_int<32> > dp_x2y4_ramDI;
	sc_signal<sc_int<32> > dp_x2y4_ramDO;
	sc_signal<bool> dp_x2y4_ramEN;
	sc_signal<bool> dp_x2y4_ramCLK;
	sc_signal<bool> dp_x2y4_ramWE;
	sc_signal<bool> dp_x2y4_ramRST;
	sc_signal<sc_uint<32> > dp_x2y4_romADDR;
	sc_signal<sc_int<32> > dp_x2y4_romDI;
	sc_signal<sc_int<32> > dp_x2y4_romDO;
	sc_signal<bool> dp_x2y4_romEN;
	sc_signal<bool> dp_x2y4_romCLK;
	sc_signal<bool> dp_x2y4_romWE;
	sc_signal<bool> dp_x2y4_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y4_xDO;
	sc_signal< sc_uint<32> > dp_x2y4_xADDR;
	sc_signal< bool > dp_x2y4_xCLK, dp_x2y4_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y5_ramADDR;
	sc_signal<sc_int<32> > dp_x2y5_ramDI;
	sc_signal<sc_int<32> > dp_x2y5_ramDO;
	sc_signal<bool> dp_x2y5_ramEN;
	sc_signal<bool> dp_x2y5_ramCLK;
	sc_signal<bool> dp_x2y5_ramWE;
	sc_signal<bool> dp_x2y5_ramRST;
	sc_signal<sc_uint<32> > dp_x2y5_romADDR;
	sc_signal<sc_int<32> > dp_x2y5_romDI;
	sc_signal<sc_int<32> > dp_x2y5_romDO;
	sc_signal<bool> dp_x2y5_romEN;
	sc_signal<bool> dp_x2y5_romCLK;
	sc_signal<bool> dp_x2y5_romWE;
	sc_signal<bool> dp_x2y5_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y5_xDO;
	sc_signal< sc_uint<32> > dp_x2y5_xADDR;
	sc_signal< bool > dp_x2y5_xCLK, dp_x2y5_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y6_ramADDR;
	sc_signal<sc_int<32> > dp_x2y6_ramDI;
	sc_signal<sc_int<32> > dp_x2y6_ramDO;
	sc_signal<bool> dp_x2y6_ramEN;
	sc_signal<bool> dp_x2y6_ramCLK;
	sc_signal<bool> dp_x2y6_ramWE;
	sc_signal<bool> dp_x2y6_ramRST;
	sc_signal<sc_uint<32> > dp_x2y6_romADDR;
	sc_signal<sc_int<32> > dp_x2y6_romDI;
	sc_signal<sc_int<32> > dp_x2y6_romDO;
	sc_signal<bool> dp_x2y6_romEN;
	sc_signal<bool> dp_x2y6_romCLK;
	sc_signal<bool> dp_x2y6_romWE;
	sc_signal<bool> dp_x2y6_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y6_xDO;
	sc_signal< sc_uint<32> > dp_x2y6_xADDR;
	sc_signal< bool > dp_x2y6_xCLK, dp_x2y6_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x2y7_ramADDR;
	sc_signal<sc_int<32> > dp_x2y7_ramDI;
	sc_signal<sc_int<32> > dp_x2y7_ramDO;
	sc_signal<bool> dp_x2y7_ramEN;
	sc_signal<bool> dp_x2y7_ramCLK;
	sc_signal<bool> dp_x2y7_ramWE;
	sc_signal<bool> dp_x2y7_ramRST;
	sc_signal<sc_uint<32> > dp_x2y7_romADDR;
	sc_signal<sc_int<32> > dp_x2y7_romDI;
	sc_signal<sc_int<32> > dp_x2y7_romDO;
	sc_signal<bool> dp_x2y7_romEN;
	sc_signal<bool> dp_x2y7_romCLK;
	sc_signal<bool> dp_x2y7_romWE;
	sc_signal<bool> dp_x2y7_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x2y7_xDO;
	sc_signal< sc_uint<32> > dp_x2y7_xADDR;
	sc_signal< bool > dp_x2y7_xCLK, dp_x2y7_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y0_ramADDR;
	sc_signal<sc_int<32> > dp_x3y0_ramDI;
	sc_signal<sc_int<32> > dp_x3y0_ramDO;
	sc_signal<bool> dp_x3y0_ramEN;
	sc_signal<bool> dp_x3y0_ramCLK;
	sc_signal<bool> dp_x3y0_ramWE;
	sc_signal<bool> dp_x3y0_ramRST;
	sc_signal<sc_uint<32> > dp_x3y0_romADDR;
	sc_signal<sc_int<32> > dp_x3y0_romDI;
	sc_signal<sc_int<32> > dp_x3y0_romDO;
	sc_signal<bool> dp_x3y0_romEN;
	sc_signal<bool> dp_x3y0_romCLK;
	sc_signal<bool> dp_x3y0_romWE;
	sc_signal<bool> dp_x3y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y0_xDO;
	sc_signal< sc_uint<32> > dp_x3y0_xADDR;
	sc_signal< bool > dp_x3y0_xCLK, dp_x3y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y1_ramADDR;
	sc_signal<sc_int<32> > dp_x3y1_ramDI;
	sc_signal<sc_int<32> > dp_x3y1_ramDO;
	sc_signal<bool> dp_x3y1_ramEN;
	sc_signal<bool> dp_x3y1_ramCLK;
	sc_signal<bool> dp_x3y1_ramWE;
	sc_signal<bool> dp_x3y1_ramRST;
	sc_signal<sc_uint<32> > dp_x3y1_romADDR;
	sc_signal<sc_int<32> > dp_x3y1_romDI;
	sc_signal<sc_int<32> > dp_x3y1_romDO;
	sc_signal<bool> dp_x3y1_romEN;
	sc_signal<bool> dp_x3y1_romCLK;
	sc_signal<bool> dp_x3y1_romWE;
	sc_signal<bool> dp_x3y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y1_xDO;
	sc_signal< sc_uint<32> > dp_x3y1_xADDR;
	sc_signal< bool > dp_x3y1_xCLK, dp_x3y1_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y2_ramADDR;
	sc_signal<sc_int<32> > dp_x3y2_ramDI;
	sc_signal<sc_int<32> > dp_x3y2_ramDO;
	sc_signal<bool> dp_x3y2_ramEN;
	sc_signal<bool> dp_x3y2_ramCLK;
	sc_signal<bool> dp_x3y2_ramWE;
	sc_signal<bool> dp_x3y2_ramRST;
	sc_signal<sc_uint<32> > dp_x3y2_romADDR;
	sc_signal<sc_int<32> > dp_x3y2_romDI;
	sc_signal<sc_int<32> > dp_x3y2_romDO;
	sc_signal<bool> dp_x3y2_romEN;
	sc_signal<bool> dp_x3y2_romCLK;
	sc_signal<bool> dp_x3y2_romWE;
	sc_signal<bool> dp_x3y2_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y2_xDO;
	sc_signal< sc_uint<32> > dp_x3y2_xADDR;
	sc_signal< bool > dp_x3y2_xCLK, dp_x3y2_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y3_ramADDR;
	sc_signal<sc_int<32> > dp_x3y3_ramDI;
	sc_signal<sc_int<32> > dp_x3y3_ramDO;
	sc_signal<bool> dp_x3y3_ramEN;
	sc_signal<bool> dp_x3y3_ramCLK;
	sc_signal<bool> dp_x3y3_ramWE;
	sc_signal<bool> dp_x3y3_ramRST;
	sc_signal<sc_uint<32> > dp_x3y3_romADDR;
	sc_signal<sc_int<32> > dp_x3y3_romDI;
	sc_signal<sc_int<32> > dp_x3y3_romDO;
	sc_signal<bool> dp_x3y3_romEN;
	sc_signal<bool> dp_x3y3_romCLK;
	sc_signal<bool> dp_x3y3_romWE;
	sc_signal<bool> dp_x3y3_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y3_xDO;
	sc_signal< sc_uint<32> > dp_x3y3_xADDR;
	sc_signal< bool > dp_x3y3_xCLK, dp_x3y3_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y4_ramADDR;
	sc_signal<sc_int<32> > dp_x3y4_ramDI;
	sc_signal<sc_int<32> > dp_x3y4_ramDO;
	sc_signal<bool> dp_x3y4_ramEN;
	sc_signal<bool> dp_x3y4_ramCLK;
	sc_signal<bool> dp_x3y4_ramWE;
	sc_signal<bool> dp_x3y4_ramRST;
	sc_signal<sc_uint<32> > dp_x3y4_romADDR;
	sc_signal<sc_int<32> > dp_x3y4_romDI;
	sc_signal<sc_int<32> > dp_x3y4_romDO;
	sc_signal<bool> dp_x3y4_romEN;
	sc_signal<bool> dp_x3y4_romCLK;
	sc_signal<bool> dp_x3y4_romWE;
	sc_signal<bool> dp_x3y4_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y4_xDO;
	sc_signal< sc_uint<32> > dp_x3y4_xADDR;
	sc_signal< bool > dp_x3y4_xCLK, dp_x3y4_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y5_ramADDR;
	sc_signal<sc_int<32> > dp_x3y5_ramDI;
	sc_signal<sc_int<32> > dp_x3y5_ramDO;
	sc_signal<bool> dp_x3y5_ramEN;
	sc_signal<bool> dp_x3y5_ramCLK;
	sc_signal<bool> dp_x3y5_ramWE;
	sc_signal<bool> dp_x3y5_ramRST;
	sc_signal<sc_uint<32> > dp_x3y5_romADDR;
	sc_signal<sc_int<32> > dp_x3y5_romDI;
	sc_signal<sc_int<32> > dp_x3y5_romDO;
	sc_signal<bool> dp_x3y5_romEN;
	sc_signal<bool> dp_x3y5_romCLK;
	sc_signal<bool> dp_x3y5_romWE;
	sc_signal<bool> dp_x3y5_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y5_xDO;
	sc_signal< sc_uint<32> > dp_x3y5_xADDR;
	sc_signal< bool > dp_x3y5_xCLK, dp_x3y5_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y6_ramADDR;
	sc_signal<sc_int<32> > dp_x3y6_ramDI;
	sc_signal<sc_int<32> > dp_x3y6_ramDO;
	sc_signal<bool> dp_x3y6_ramEN;
	sc_signal<bool> dp_x3y6_ramCLK;
	sc_signal<bool> dp_x3y6_ramWE;
	sc_signal<bool> dp_x3y6_ramRST;
	sc_signal<sc_uint<32> > dp_x3y6_romADDR;
	sc_signal<sc_int<32> > dp_x3y6_romDI;
	sc_signal<sc_int<32> > dp_x3y6_romDO;
	sc_signal<bool> dp_x3y6_romEN;
	sc_signal<bool> dp_x3y6_romCLK;
	sc_signal<bool> dp_x3y6_romWE;
	sc_signal<bool> dp_x3y6_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y6_xDO;
	sc_signal< sc_uint<32> > dp_x3y6_xADDR;
	sc_signal< bool > dp_x3y6_xCLK, dp_x3y6_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x3y7_ramADDR;
	sc_signal<sc_int<32> > dp_x3y7_ramDI;
	sc_signal<sc_int<32> > dp_x3y7_ramDO;
	sc_signal<bool> dp_x3y7_ramEN;
	sc_signal<bool> dp_x3y7_ramCLK;
	sc_signal<bool> dp_x3y7_ramWE;
	sc_signal<bool> dp_x3y7_ramRST;
	sc_signal<sc_uint<32> > dp_x3y7_romADDR;
	sc_signal<sc_int<32> > dp_x3y7_romDI;
	sc_signal<sc_int<32> > dp_x3y7_romDO;
	sc_signal<bool> dp_x3y7_romEN;
	sc_signal<bool> dp_x3y7_romCLK;
	sc_signal<bool> dp_x3y7_romWE;
	sc_signal<bool> dp_x3y7_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x3y7_xDO;
	sc_signal< sc_uint<32> > dp_x3y7_xADDR;
	sc_signal< bool > dp_x3y7_xCLK, dp_x3y7_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x4y0_ramADDR;
	sc_signal<sc_int<32> > dp_x4y0_ramDI;
	sc_signal<sc_int<32> > dp_x4y0_ramDO;
	sc_signal<bool> dp_x4y0_ramEN;
	sc_signal<bool> dp_x4y0_ramCLK;
	sc_signal<bool> dp_x4y0_ramWE;
	sc_signal<bool> dp_x4y0_ramRST;
	sc_signal<sc_uint<32> > dp_x4y0_romADDR;
	sc_signal<sc_int<32> > dp_x4y0_romDI;
	sc_signal<sc_int<32> > dp_x4y0_romDO;
	sc_signal<bool> dp_x4y0_romEN;
	sc_signal<bool> dp_x4y0_romCLK;
	sc_signal<bool> dp_x4y0_romWE;
	sc_signal<bool> dp_x4y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x4y0_xDO;
	sc_signal< sc_uint<32> > dp_x4y0_xADDR;
	sc_signal< bool > dp_x4y0_xCLK, dp_x4y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x4y1_ramADDR;
	sc_signal<sc_int<32> > dp_x4y1_ramDI;
	sc_signal<sc_int<32> > dp_x4y1_ramDO;
	sc_signal<bool> dp_x4y1_ramEN;
	sc_signal<bool> dp_x4y1_ramCLK;
	sc_signal<bool> dp_x4y1_ramWE;
	sc_signal<bool> dp_x4y1_ramRST;
	sc_signal<sc_uint<32> > dp_x4y1_romADDR;