📄 cache_braml2.cpp
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/* * TU Eindhoven * Eindhoven, The Netherlands * * Name : cache_braml2.h * * Author : A.S.Slusarczyk@tue.nl * * Date : * * Function : Cache interface to the main memory in BlockRAM * * */#include "cache_braml2.h"void CACHE_BRAML2_WRAP::reg(){ if( en.read() ){ word = offset.read(); }}void CACHE_BRAML2_WRAP::in(){ bool clk_v = clk.read(); bool en_v = en.read(); bool we_v = we.read(); sc_uint<2> off = offset.read(); sc_int<32> din_v = din.read(); sc_bv<9> addr0, addr1; sc_bv<TAG_BITS> tag_in_v = tagi.read(); sc_bv<4> tag3, tag2, tag1, tag0; addr0 = (index.read(), sc_bv<1>(0)); addr1 = (index.read(), sc_bv<1>(1)); ADDRA0.write( sc_uint<9>(addr0) ); ADDRB0.write( sc_uint<9>(addr1) ); ADDRA1.write( sc_uint<9>(addr0) ); ADDRB1.write( sc_uint<9>(addr1) ); DIA0.write(din_v); DIB0.write(din_v); DIA1.write(din_v); DIB1.write(din_v); WEA0.write(false); WEB0.write(false); WEA1.write(false); WEB1.write(false); switch(off){ case 1 : WEB0.write(we_v); break; case 2 : WEA1.write(we_v); break; case 3 : WEB1.write(we_v); break; default : WEA0.write(we_v); break; } tag3[3] = valid_in.read(); tag3.range(2,0) = tag_in_v.range(14,12); tag2 = tag_in_v.range(11,8); tag1 = tag_in_v.range(7,4); tag0 = tag_in_v.range(3,0); DIPB1.write( tag3 ); DIPA1.write( tag2 ); DIPB0.write( tag1 ); DIPA0.write( tag0 ); ENA0.write(en_v); ENB0.write(en_v); ENA1.write(en_v); ENB1.write(en_v); CLKA0.write(clk_v); CLKB0.write(clk_v); CLKA1.write(clk_v); CLKB1.write(clk_v); SSRA0.write(false); SSRB0.write(false); SSRA1.write(false); SSRB1.write(false); }void CACHE_BRAML2_WRAP::out(){ sc_bv<32> data; switch(word.read()){ case 1 : data = DOB0.read(); break; case 2 : data = DOA1.read(); break; case 3 : data = DOB1.read(); break; default : data = DOA0.read(); break; } dout.write(data); rdy.write(true);}
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