cache_ctrl.h

国外开源的一个片上网络系统的源代码

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   cache_ctrl.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Cache control logic
 *
 *
 */

#ifndef CACHE_CTRL_H_INCLUDED
#define CACHE_CTRL_H_INCLUDED

#include <systemc.h>
#include "cache_dim.h"
#include "mips.h"

SC_MODULE(CACHE_DIN_SELECT)
{
  sc_in< sc_bv<32> > din_data, din_data_reg;
  sc_in< sc_bv<32> > din_fetch;
  sc_in< sc_bv<32> > din_out;
  
  sc_in< bool > rewrite, rewrite_valid, byte_rpl;
  sc_in< sc_bv<W_MEMWRITE> > w;
  sc_in< sc_uint<2> > byte;
  sc_in< bool > fetch_word_rdy;
  
  sc_out< bool > valid;
  sc_out< sc_bv<32> > data;
  
  void select();
  SC_CTOR(CACHE_DIN_SELECT){
	SC_METHOD(select);
	sensitive << din_data << din_data_reg << din_fetch << din_out 
			  << w << byte << fetch_word_rdy 
			  << rewrite << rewrite_valid << byte_rpl;
  }
};


SC_MODULE(CACHE_ADDR_SPLIT)
{
  sc_in< sc_bv<32> > addr;  
  sc_in< sc_bv<32> > addr_reg;
  
  sc_in< sc_uint<2> > fetch_word;
  sc_in< bool > fetch_word_rdy;
  
  sc_in< sc_bv<TAG_BITS> > tag_rewrite;
  sc_in< bool > rewrite;

  sc_out< sc_bv<TAG_BITS> > tag, tag_reg;
  sc_out< sc_bv<INDEX_BITS> > index, index_reg;
  sc_out< sc_bv<OFFSET_BITS> > offset, offset_reg;
  sc_out< sc_uint<2> > byte, byte_reg;

  
  void split();
  SC_CTOR(CACHE_ADDR_SPLIT){
	SC_METHOD(split);
	sensitive << addr << addr_reg 
			  << fetch_word << fetch_word_rdy 
			  << rewrite << tag_rewrite;
  }
};

SC_MODULE(CACHE_BYTE_SELECT)
{
  sc_in< sc_bv<32> > din;  
  sc_in< sc_bv<W_MEMREAD> > r;
  sc_in< sc_uint<2> > byte;
  sc_out< sc_bv<32> > dout;
 
  void select();
  SC_CTOR(CACHE_BYTE_SELECT){
	SC_METHOD(select);
	sensitive << din << byte << r;
  }
};


SC_MODULE(CACHE_MISS_CTRL)
{
  sc_in< bool > clk;
  sc_in< sc_bv<1> > en;
  
  sc_in< bool > cache_valid;
  sc_in< sc_bv<TAG_BITS> > cache_tag;
  sc_in< sc_bv<TAG_BITS> > addr_tag;
  sc_out< bool > cache_en, cache_we;
  
  sc_in< sc_bv< W_MEMWRITE > > w;
  sc_in< sc_bv< W_MEMREAD > > r;  
  sc_out< bool > miss_wait;
  
  sc_out< bool > rewrite, byte_rpl;
  sc_out< bool > current_reg;

  sc_signal< bool > waiting;
  sc_signal< bool > miss;

  sc_out< bool > mem_ww, mem_wb, mem_r;
  sc_in< bool > mem_rdy;
  sc_in< sc_bv<32> > din, addr;
  sc_out< sc_bv<32> > mem_din, mem_addr;
  
  
  enum state { MEMORY, FETCH, REREAD_WORD, WAIT_FETCH, WAIT_WRITE };
  sc_signal< unsigned > current_state, next_state;
  
  enum op { NONE, R, WW, WB };
  sc_signal< unsigned > operation, n_operation;

  sc_signal< sc_uint<2> > next_fetch_word;
  sc_signal< bool > word_inc, word_clr;

  sc_out< sc_uint<2> > fetch_word;
  sc_out< bool > fetch_word_rdy;
  
  sc_signal< bool > start_write;
  sc_signal< bool > write_in_progress;
  
  void logic();
  void change_state();  
  void miss_detect();
  void write_progress();
  void fetch_word_reg();
  
  SC_CTOR(CACHE_MISS_CTRL){
	SC_METHOD(logic);
	sensitive << current_state << operation << waiting 
			  << write_in_progress << next_fetch_word
			  << miss << mem_rdy
			  << din << addr << r << w << en;
	  

	SC_METHOD(change_state);
	sensitive_pos << clk;
	
	SC_METHOD(miss_detect);
	sensitive << cache_valid << cache_tag << addr_tag;
	
	SC_METHOD(write_progress);
	sensitive_pos << clk;

	SC_METHOD(fetch_word_reg);
	sensitive_pos << clk;
	
	SC_METHOD(mr);
	sensitive << mem_rdy;
  }
  void mr(){
	//cout << "mem_rdy=" << mem_rdy.read() << " " << sc_time_stamp() << endl;
  }
};


#endif