mmips.h

国外开源的一个片上网络系统的源代码

	dmem->mem_rdy(dcache_rdy);
	
#else
	dmem = new BRAM16K("data_memory");		
#endif

#ifdef USEXRAM
	xram = new XRAM("xram");

	xram->DI( xDI );
	xram->DO( xDO );
	xram->CLK( xCLK );
	xram->WE( xWE );
	xram->ADDR( xADDR );

	signal_dbg = new SIGNAL_DBG("signal_dbg");

	signal_dbg->sig32( bus_pc );
	signal_dbg->clock(clock);
	signal_dbg->enable(enable);
	signal_dbg->reset(reset);
	signal_dbg->clk(clk);
	signal_dbg->ctrl_enable(bus_ctrl_enable);
	signal_dbg->ctrl_hazard_pcwrite(bus_hazard_pcwrite);
	signal_dbg->ctrl_hazard_ifidwrite(bus_hazard_ifidwrite);
	signal_dbg->ctrl_hazard_hazard(bus_hazard_hazard);
	signal_dbg->pipe_en(bus_pipe_en);
	signal_dbg->dmem_en(bus_dmem_en);
	signal_dbg->imem_en(bus_imem_en);
	signal_dbg->decoder_nb_instr_25_21(bus_decoder_nb_instr_25_21);
	signal_dbg->decoder_nb_instr_20_16(bus_decoder_nb_instr_20_16);

	signal_dbg->DO( xDI );

#endif

	
	registers = new REGFILE16("registers");	
	alu = new ALU("alu");
	aluctrl = new ALUCTRL("aluctrl");	
	imm2word = new IMM2WORD("imm2word");
	signextendbyte = new SIGNEXTEND_BYTE("signextendbyte");
	shiftleft = new SHIFTLEFT("shiftleft");
	shiftleft_jmp = new SHIFTLEFT("shiftleft_jmp");
	ctrl = new CTRL("ctrl");
	decoder = new DECODER("decoder");

	mux7 = new MUX2("mux7");
	decoder_nb = new DECODER_NBUF("decoder_nb");
	
	mux1 = new MUX2("mux1");
	mux2 = new MUX2("mux2");
	mux3 = new MUX3("mux3");
	mux4 = new MUX3_AWORDREG("mux4");
	mux5 = new MUX3("mux5");
	mux6 = new MUX2("mux6");

	clkdist = new CLKDIST("clkdist");
	
	/*
	 *	Connections
	 */
	// Hazard detection unit
	hazard->MEMWBRegWrite(bus_mem_ctrl_wb_regwrite);
	hazard->EXMEMRegWrite(bus_ex_ctrl_wb_regwrite);
	hazard->IDEXRegWrite(bus_id_ctrl_wb_regwrite);
	hazard->IDEXRegDst(bus_id_ctrl_ex_regdst);
	hazard->IDEXWriteRegisterRt(bus_id_instr_20_16);
	hazard->IDEXWriteRegisterRd(bus_id_instr_15_11);
	hazard->EXMEMWriteRegister(bus_ex_regdst_addr);
	hazard->MEMWBWriteRegister(bus_mem_regdst_addr);
	hazard->Instr(bus_if_instr);
	hazard->BranchOp(bus_id_ctrl_mem_branch);
	hazard->PCWrite(bus_hazard_pcwrite);
	hazard->IFIDWrite(bus_hazard_ifidwrite);
	hazard->Hazard(bus_hazard_hazard);
	hazard->enable(bus_ctrl_enable);

	hazard->dmem_wait(bus_dmem_wait);
	hazard->imem_wait(bus_imem_wait);
	hazard->dmem_en(bus_dmem_en);
	hazard->imem_en(bus_imem_en);
	hazard->pipe_en(bus_pipe_en);


	// Hazard handling unit
	hazard_ctrl->Hazard(bus_hazard_hazard);
	hazard_ctrl->CtrlRegDst(bus_ctrl2hazard_regdst);
	hazard_ctrl->CtrlRegValue(bus_ctrl2hazard_regvalue);
	hazard_ctrl->CtrlTarget(bus_ctrl2hazard_target);
	hazard_ctrl->CtrlBranch(bus_ctrl2hazard_branch);
	hazard_ctrl->CtrlMemRead(bus_ctrl2hazard_memread);
	hazard_ctrl->CtrlMemtoReg(bus_ctrl2hazard_memtoreg);
	hazard_ctrl->CtrlALUop(bus_ctrl2hazard_aluop);
	hazard_ctrl->CtrlMemWrite(bus_ctrl2hazard_memwrite);
	hazard_ctrl->CtrlALUSrc(bus_ctrl2hazard_alusrc);
	hazard_ctrl->CtrlRegWrite(bus_ctrl2hazard_regwrite);
	hazard_ctrl->RegDst(bus_ctrl_regdst);
	hazard_ctrl->RegValue(bus_ctrl_regvalue);
	hazard_ctrl->Target(bus_ctrl_target);
	hazard_ctrl->Branch(bus_ctrl_branch);
	hazard_ctrl->MemRead(bus_ctrl_memread);
	hazard_ctrl->MemtoReg(bus_ctrl_memtoreg);
	hazard_ctrl->ALUop(bus_ctrl_aluop);
	hazard_ctrl->MemWrite(bus_ctrl_memwrite);
	hazard_ctrl->ALUSrc(bus_ctrl_alusrc);
	hazard_ctrl->RegWrite(bus_ctrl_regwrite);
	
	// Pipeline registers
	// Instruction fecth -> Instruction decode
	if_pc->in(bus_add1);
	if_pc->out(bus_if_pc);
	if_pc->w(bus_hazard_ifidwrite);
	if_pc->clk(clk);
	if_pc->rst(reset);
	 
	if_instr->in(bus_imem_1); 
	if_instr->out(bus_if_instr);
	if_instr->w(bus_hazard_ifidwrite);
	if_instr->clk(clk);
	if_instr->rst(reset);
	
	// Instruction decode -> Execution
	id_pc->in(bus_if_pc);
	id_pc->out(bus_id_pc);
	id_pc->w(bus_pipe_en);
	id_pc->clk(clk);
	id_pc->rst(reset);
	 
	id_data_reg1->in(bus_registers_1); 
	id_data_reg1->out(bus_id_data_reg1);
	id_data_reg1->w(bus_pipe_en);
	id_data_reg1->clk(clk);
	id_data_reg1->rst(reset);
	
	id_data_reg2->in(bus_registers_2); 
	id_data_reg2->out(bus_id_data_reg2);
	id_data_reg2->w(bus_pipe_en);
	id_data_reg2->clk(clk);
	id_data_reg2->rst(reset);

	id_immediate->in(bus_imm2word);
	id_immediate->out(bus_id_immediate);
	id_immediate->w(bus_pipe_en);
	id_immediate->clk(clk);
	id_immediate->rst(reset);

	id_instr_25_0->in(bus_decoder_instr_25_0);
	id_instr_25_0->out(bus_id_instr_25_0);
	id_instr_25_0->w(bus_pipe_en);
	id_instr_25_0->clk(clk);
	id_instr_25_0->rst(reset);
	 
	id_instr_20_16->in(bus_decoder_instr_20_16);
	id_instr_20_16->out(bus_id_instr_20_16);
	id_instr_20_16->w(bus_pipe_en);
	id_instr_20_16->clk(clk);
	id_instr_20_16->rst(reset);
	 
	id_instr_15_11->in(bus_decoder_instr_15_11);
	id_instr_15_11->out(bus_id_instr_15_11);
	id_instr_15_11->w(bus_pipe_en);
	id_instr_15_11->clk(clk);
	id_instr_15_11->rst(reset);

	id_instr_10_6->in(bus_decoder_instr_10_6);
	id_instr_10_6->out(bus_id_instr_10_6);
	id_instr_10_6->w(bus_pipe_en);
	id_instr_10_6->clk(clk);
	id_instr_10_6->rst(reset);

	id_instr_5_0->in(bus_decoder_instr_5_0);
	id_instr_5_0->out(bus_id_instr_5_0);
	id_instr_5_0->w(bus_pipe_en);
	id_instr_5_0->clk(clk);
	id_instr_5_0->rst(reset);

	id_ctrl_ex_alusrc->in(bus_ctrl_alusrc); 
	id_ctrl_ex_alusrc->out(bus_id_ctrl_ex_alusrc); 
	id_ctrl_ex_alusrc->w(bus_pipe_en); 
	id_ctrl_ex_alusrc->clk(clk);
	id_ctrl_ex_alusrc->rst(reset); 

	id_ctrl_ex_aluop->in(bus_ctrl_aluop);
	id_ctrl_ex_aluop->out(bus_id_ctrl_ex_aluop);
	id_ctrl_ex_aluop->w(bus_pipe_en);
	id_ctrl_ex_aluop->clk(clk);
	id_ctrl_ex_aluop->rst(reset);
	 
	id_ctrl_ex_regdst->in(bus_ctrl_regdst);
	id_ctrl_ex_regdst->out(bus_id_ctrl_ex_regdst);
	id_ctrl_ex_regdst->w(bus_pipe_en);
	id_ctrl_ex_regdst->clk(clk);
	id_ctrl_ex_regdst->rst(reset);

	id_ctrl_ex_regvalue->in(bus_ctrl_regvalue);
	id_ctrl_ex_regvalue->out(bus_id_ctrl_ex_regvalue);
	id_ctrl_ex_regvalue->w(bus_pipe_en);
	id_ctrl_ex_regvalue->clk(clk);
	id_ctrl_ex_regvalue->rst(reset);

	id_ctrl_ex_target->in(bus_ctrl_target);
	id_ctrl_ex_target->out(bus_id_ctrl_ex_target);
	id_ctrl_ex_target->w(bus_pipe_en);
	id_ctrl_ex_target->clk(clk);
	id_ctrl_ex_target->rst(reset);
	 
	id_ctrl_mem_branch->in(bus_ctrl_branch); 
	id_ctrl_mem_branch->out(bus_id_ctrl_mem_branch); 
	id_ctrl_mem_branch->w(bus_pipe_en); 
	id_ctrl_mem_branch->clk(clk);
	id_ctrl_mem_branch->rst(reset); 

	id_ctrl_mem_memwrite->in(bus_ctrl_memwrite); 
	id_ctrl_mem_memwrite->out(bus_id_ctrl_mem_memwrite); 
	id_ctrl_mem_memwrite->w(bus_pipe_en); 
	id_ctrl_mem_memwrite->clk(clk);
	id_ctrl_mem_memwrite->rst(reset); 

	id_ctrl_mem_memread->in(bus_ctrl_memread); 
	id_ctrl_mem_memread->out(bus_id_ctrl_mem_memread); 
	id_ctrl_mem_memread->w(bus_pipe_en); 
	id_ctrl_mem_memread->clk(clk);
	id_ctrl_mem_memread->rst(reset); 

	id_ctrl_wb_regwrite->in(bus_ctrl_regwrite); 
	id_ctrl_wb_regwrite->out(bus_id_ctrl_wb_regwrite); 
	id_ctrl_wb_regwrite->w(bus_pipe_en); 
	id_ctrl_wb_regwrite->clk(clk);
	id_ctrl_wb_regwrite->rst(reset); 

	id_ctrl_wb_memtoreg->in(bus_ctrl_memtoreg); 
	id_ctrl_wb_memtoreg->out(bus_id_ctrl_wb_memtoreg); 
	id_ctrl_wb_memtoreg->w(bus_pipe_en); 
	id_ctrl_wb_memtoreg->clk(clk);
	id_ctrl_wb_memtoreg->rst(reset); 

	// Execution -> Memory stage
	ex_regdst_addr->in(bus_mux4);
	ex_regdst_addr->out(bus_ex_regdst_addr);
	ex_regdst_addr->w(bus_pipe_en);
	ex_regdst_addr->clk(clk);
	ex_regdst_addr->rst(reset);
	 
	ex_alu_result->in(bus_mux6);
	ex_alu_result->out(bus_ex_alu_result);
	ex_alu_result->w(bus_pipe_en);
	ex_alu_result->clk(clk);
	ex_alu_result->rst(reset);
		 
	ex_ctrl_wb_regwrite->in(bus_id_ctrl_wb_regwrite);
	ex_ctrl_wb_regwrite->out(bus_ex_ctrl_wb_regwrite);
	ex_ctrl_wb_regwrite->w(bus_pipe_en);
	ex_ctrl_wb_regwrite->clk(clk);
	ex_ctrl_wb_regwrite->rst(reset);
	 
	ex_ctrl_wb_memtoreg->in(bus_id_ctrl_wb_memtoreg); 
	ex_ctrl_wb_memtoreg->out(bus_ex_ctrl_wb_memtoreg); 
	ex_ctrl_wb_memtoreg->w(bus_pipe_en); 
	ex_ctrl_wb_memtoreg->clk(clk);
	ex_ctrl_wb_memtoreg->rst(reset); 

	// Memory stage -> Write back stage
	mem_dmem_data->in(bus_dmem_1); 
	mem_dmem_data->out(bus_mem_dmem_data);
	mem_dmem_data->w(bus_pipe_en); 
	mem_dmem_data->clk(clk);
	mem_dmem_data->rst(reset); 

	mem_alu_result->in(bus_ex_alu_result);
	mem_alu_result->out(bus_mem_alu_result);
	mem_alu_result->w(bus_pipe_en);
	mem_alu_result->clk(clk);
	mem_alu_result->rst(reset);
	 
	mem_regdst_addr->in(bus_ex_regdst_addr); 
	mem_regdst_addr->out(bus_mem_regdst_addr); 
	mem_regdst_addr->w(bus_pipe_en); 
	mem_regdst_addr->clk(clk);
	mem_regdst_addr->rst(reset); 

	mem_ctrl_wb_regwrite->in(bus_ex_ctrl_wb_regwrite);
	mem_ctrl_wb_regwrite->out(bus_mem_ctrl_wb_regwrite);
	mem_ctrl_wb_regwrite->w(bus_pipe_en);
	mem_ctrl_wb_regwrite->clk(clk);
	mem_ctrl_wb_regwrite->rst(reset);
	 
	mem_ctrl_wb_memtoreg->in(bus_ex_ctrl_wb_memtoreg); 
	mem_ctrl_wb_memtoreg->out(bus_mem_ctrl_wb_memtoreg); 
	mem_ctrl_wb_memtoreg->w(bus_pipe_en); 
	mem_ctrl_wb_memtoreg->clk(clk);
	mem_ctrl_wb_memtoreg->rst(reset); 

	// Program counter
	pc->in(bus_mux1);
	pc->out(bus_pc);
	pc->w(bus_hazard_pcwrite);
	pc->clk(clk);
	pc->rst(reset);
	
	// Add 1 (PC + 4)
	add1->a(bus_pc);
	add1->b(bus_ctrl_c4);
	add1->r(bus_add1);
	
	// Add 2 (add1 + shiftleft)
	add2->a(bus_id_pc);
	add2->b(bus_shiftleft);
	add2->r(bus_add2);
	
	// Shiftleft jump target
	shiftleft_jmp->in(bus_id_instr_25_0);
	shiftleft_jmp->out(bus_shiftleft_jmp);
	
	// Mux 5 (Select target for branch)
	mux5->in0(bus_add2);
	mux5->in1(bus_shiftleft_jmp);
	mux5->in2(bus_id_data_reg1);
	mux5->sel(bus_id_ctrl_ex_target);
	mux5->out(bus_mux5);
	
	// Mux 1 (add1 or add2)
	mux1->in0(bus_add1);
	mux1->in1(bus_mux5);
	mux1->sel(bus_branch);
	mux1->out(bus_mux1);
	
	// Shift left
	shiftleft->in(bus_id_immediate);
	shiftleft->out(bus_shiftleft);
	
	// Sign extend
	imm2word->in(bus_decoder_instr_15_0);
    	imm2word->signextend(bus_ctrl_signextend);
	imm2word->out(bus_imm2word);

	// Decoder (Select correct part of instruction for registerfile)
	decoder->instr(bus_if_instr);
	decoder->instr_31_26(bus_decoder_instr_31_26);
	decoder->instr_25_0(bus_decoder_instr_25_0);
	decoder->instr_25_21(bus_decoder_instr_25_21);
	decoder->instr_20_16(bus_decoder_instr_20_16);
	decoder->instr_15_11(bus_decoder_instr_15_11);
	decoder->instr_15_0(bus_decoder_instr_15_0);
	decoder->instr_10_6(bus_decoder_instr_10_6);
	decoder->instr_5_0(bus_decoder_instr_5_0);
	
	// Mux 4 (Select address for write to registerfile)
	mux4->in0(bus_id_instr_20_16);
	mux4->in1(bus_id_instr_15_11);
	mux4->in2(bus_ctrl_c31);
	mux4->sel(bus_id_ctrl_ex_regdst);
	mux4->out(bus_mux4);
	
	// ALU
	alu->a(bus_id_data_reg1);
	alu->b(bus_mux2);
	alu->r(bus_alu_result);
	alu->z(bus_alu_zero);
	alu->ctrl(bus_aluctrl);
	
	// MUX 6 (Select value for register / memory write)
	// Can be 'next PC' or 'ALU result'
	mux6->in0(bus_alu_result);
	mux6->in1(bus_if_pc);
	mux6->sel(bus_id_ctrl_ex_regvalue);
	mux6->out(bus_mux6); 
	
	// Mux 2 (Registerfile or signextend)
	mux2->in0(bus_id_data_reg2);
	mux2->in1(bus_id_immediate);
	mux2->sel(bus_id_ctrl_ex_alusrc);
	mux2->out(bus_mux2);
	
	// ALU ctrl
	aluctrl->ALUop(bus_id_ctrl_ex_aluop);
	aluctrl->functionCode(bus_id_instr_5_0);
	aluctrl->Shamt(bus_id_instr_10_6);
	aluctrl->ALUctrl(bus_aluctrl);
	
	// Signextend byte
	signextendbyte->in(bus_mem_dmem_data);
	signextendbyte->out(bus_signextendbyte);
	
	// Mux 3 (ALU result or memory result to register)
	mux3->in0(bus_mem_alu_result);
	mux3->in1(bus_mem_dmem_data);
	mux3->in2(bus_signextendbyte);
	mux3->sel(bus_mem_ctrl_wb_memtoreg);
	mux3->out(bus_mux3);
	
	// Branch controller
	branch_ctrl->BranchOp(bus_id_ctrl_mem_branch);
	branch_ctrl->AluZero(bus_alu_zero);
	branch_ctrl->Branch(bus_branch);
	
	// Registerfile
	mux7->in0( bus_if_instr );
	mux7->in1( bus_imem_1 );
	mux7->sel( bus_hazard_ifidwrite );
	mux7->out( bus_mux7 );
	
	decoder_nb->instr( bus_mux7 );
	decoder_nb->instr_25_21( bus_decoder_nb_instr_25_21 );
	decoder_nb->instr_20_16( bus_decoder_nb_instr_20_16 );

	registers->r_addr_reg1(bus_decoder_nb_instr_25_21);
	registers->r_addr_reg2(bus_decoder_nb_instr_20_16);
	registers->w_addr_reg(bus_mem_regdst_addr);
	registers->r_data_reg1(bus_registers_1);
	registers->r_data_reg2(bus_registers_2);
	registers->w_data_reg(bus_mux3);
	registers->w(bus_mem_ctrl_wb_regwrite);
	registers->clk(clk);
	
	// Instruction Memory 
	imem->addr(bus_mux1);
	imem->dout(bus_imem_1);
	imem->clk(clk);
	imem->en(bus_imem_en);
	imem->memwait(bus_imem_wait);

#ifdef ICACHE
	imem->w(c0_imem_w);
	imem->r(c1_imem_r);
	imem->din(c0_imem_din);	
#endif

#ifndef ICACHE
	imem->dbgDO(romDO);
	imem->dbgADDR(romADDR);
	imem->dbgDI(romDI);
	imem->dbgEN(romEN);
	imem->dbgCLK(romCLK);
	imem->dbgWE(romWE);
	imem->dbgRST(romRST);	
#endif

	// Data memory
	dmem->addr(bus_ram_addr);
	dmem->dout(bus_ram_dout);
	dmem->r(bus_ram_r);
	dmem->din(bus_ram_din);
	dmem->w(bus_ram_w);
	dmem->memwait(bus_ram_wait);
	dmem->clk(clk);
	dmem->en(bus_dmem_en);

#ifndef DCACHE
	dmem->dbgDO(ramDO);
	dmem->dbgADDR(ramADDR);
	dmem->dbgDI(ramDI);
	dmem->dbgEN(ramEN);
	dmem->dbgCLK(ramCLK);
	dmem->dbgWE(ramWE);
	dmem->dbgRST(ramRST);	
#endif
	
	// memory-mapped device and the wrapper
	memdev = new MEMDEV("memdev");

	memdev->clk(clk);
	memdev->a_read(bus_mux6);
	memdev->a_read_reg(bus_ex_alu_result);
	memdev->d_write(bus_id_data_reg2);
	memdev->r(bus_id_ctrl_mem_memread);
	memdev->w(bus_id_ctrl_mem_memwrite);
	memdev->d_read(bus_dmem_1);
	
	memdev->ram_dout(bus_ram_dout);
	memdev->ram_wait(bus_ram_wait);
	memdev->ram_addr(bus_ram_addr);
	memdev->ram_din(bus_ram_din);
	memdev->ram_w(bus_ram_w);
	memdev->ram_r(bus_ram_r);
	
	memdev->dev_dout( dev_din );
	memdev->dev_din( dev_dout );
	memdev->dev_w( dev_w );
	memdev->dev_r( dev_r );
	memdev->dev_wdata( dev_wdata );
	memdev->dev_waddr( dev_waddr );
	memdev->dev_send_eop( dev_send_eop );
	memdev->dev_rcv_eop( dev_rcv_eop );

	memdev->dev_rdyr( dev_rdyr );
	memdev->dev_rdyw( dev_rdyw );
	memdev->dmem_wait( bus_dmem_wait );
	
	// Controller
	ctrl->FunctionCode(bus_decoder_instr_5_0);
	ctrl->Opcode(bus_decoder_instr_31_26);
	ctrl->ALUop(bus_ctrl2hazard_aluop);
	ctrl->ALUSrc(bus_ctrl2hazard_alusrc);
	ctrl->Branch(bus_ctrl2hazard_branch);
	ctrl->c1(bus_ctrl_c1);
	ctrl->en(bus_ctrl_enable);
	ctrl->c31(bus_ctrl_c31);
	ctrl->c4(bus_ctrl_c4);
	ctrl->MemRead(bus_ctrl2hazard_memread);
	ctrl->MemtoReg(bus_ctrl2hazard_memtoreg);
	ctrl->MemWrite(bus_ctrl2hazard_memwrite);
	ctrl->RegDst(bus_ctrl2hazard_regdst);
	ctrl->RegValue(bus_ctrl2hazard_regvalue);
	ctrl->RegWrite(bus_ctrl2hazard_regwrite);
	ctrl->SignExtend(bus_ctrl_signextend);
	ctrl->Target(bus_ctrl2hazard_target);
	ctrl->enable(enable);

	clkdist->clkin(clock);
	clkdist->clkout(clk);  
  }
	
};


#endif