mmips.h

国外开源的一个片上网络系统的源代码

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   mmips.h
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   Top-level mMIPS module
 */


#ifndef MMIPS_H_INCLUDED
#define MMIPS_H_INCLUDED

#include "add.h"
#include "aluctrl.h"
#include "alu.h"
#include "branch.h"
#include "ctrl.h"
#include "decoder.h"
#include "hazard.h"
#include "imm2word.h"
#include "mux.h"
#include "register.h"
#include "shift.h"
#include "signextend.h"

#include "bram16k.h"
#include "brom16k.h"
#include "bregisterfile16.h"

#include "memdev.h"

#ifdef CACHE
#define ICACHE
#define DCACHE
#include "cache.h"
#endif

#ifdef USEXRAM
#include "xram.h"
#endif

SC_MODULE(CLKDIST){
  sc_in<bool> clkin;
  sc_out<bool> clkout;
  
  SC_CTOR(CLKDIST){
	SC_METHOD(clk);
	sensitive << clkin;
  }
  
  void clk(){
	clkout.write(clkin.read());
  }
  
};

SC_MODULE(mMIPS)
{

  sc_in<bool> clock;
  sc_in<bool> enable;
  sc_in<bool> reset;

  sc_signal<bool> clk;

  /*
   *	SIGNALS
   */
  
  sc_out< sc_bv<DWORD> >          bus_pc;
  
  
  // Data signals
  sc_signal< sc_bv<DWORD> 		> bus_mux1;
  sc_signal< sc_bv<DWORD> 		> bus_mux2;
  sc_signal< sc_bv<DWORD> 		> bus_mux3;
  sc_signal< sc_bv<AWORDREG>		> bus_mux4;
  sc_signal< sc_bv<DWORD> 		> bus_mux5;
  sc_signal< sc_bv<DWORD> 		> bus_mux6;

  sc_signal< sc_bv<6> 			> bus_decoder_instr_31_26;
  sc_signal< sc_bv<DWORD> 		> bus_decoder_instr_25_0;
  sc_signal< sc_bv<AWORDREG> 		> bus_decoder_instr_25_21;
  sc_signal< sc_bv<AWORDREG> 		> bus_decoder_instr_20_16;
  sc_signal< sc_bv<AWORDREG> 		> bus_decoder_instr_15_11;
  sc_signal< sc_bv<16> 			> bus_decoder_instr_15_0;
  sc_signal< sc_bv<5> 			> bus_decoder_instr_10_6;
  sc_signal< sc_bv<6> 			> bus_decoder_instr_5_0;
		
  sc_signal< sc_bv<DWORD> 		> bus_add1;
  sc_signal< sc_bv<DWORD> 		> bus_add2;

  sc_signal< sc_bv<DWORD> 		> bus_shiftleft;
  sc_signal< sc_bv<DWORD> 		> bus_shiftleft_jmp;

  sc_signal< sc_bv<DWORD> 		> bus_imm2word;
  sc_signal< sc_bv<DWORD> 		> bus_signextendbyte;

  sc_signal< sc_bv<DWORD> 		> bus_imem_1;
	
  sc_signal< sc_bv<DWORD> 		> bus_dmem_1;
	
  sc_signal< sc_bv<DWORD> 		> bus_alu_result;
  sc_signal< sc_bv<1> 			> bus_alu_zero;

  sc_signal< sc_bv<DWORD> 		> bus_registers_1;
  sc_signal< sc_bv<DWORD> 		> bus_registers_2;
	
  // Control signals
  sc_signal< sc_bv<W_REGDST>		> bus_ctrl_regdst;
  sc_signal< sc_bv<W_REGVAL>		> bus_ctrl_regvalue;
  sc_signal< sc_bv<W_TARGET>		> bus_ctrl_target;
  sc_signal< sc_bv<W_BRANCHOP>	> bus_ctrl_branch;
  sc_signal< sc_bv<W_MEMREAD>		> bus_ctrl_memread;
  sc_signal< sc_bv<W_MEMTOREG>	> bus_ctrl_memtoreg;
  sc_signal< sc_bv<W_ALUOP>		> bus_ctrl_aluop;
  sc_signal< sc_bv<W_MEMWRITE>	> bus_ctrl_memwrite;
  sc_signal< sc_bv<W_ALUSRC>		> bus_ctrl_alusrc;
  sc_signal< sc_bv<W_REGWRITE>	> bus_ctrl_regwrite;
  sc_signal< sc_bv<W_SIGNEXTEND>    > bus_ctrl_signextend;   
  sc_signal< sc_bv<DWORD>			> bus_ctrl_c4;
  sc_signal< sc_bv<1>				> bus_ctrl_c1;
  sc_signal< sc_bv<AWORDREG>		> bus_ctrl_c31;
  sc_signal< sc_bv<1> >               bus_ctrl_enable;

  sc_signal< sc_bv<1> >               bus_pipe_en, bus_dmem_en, bus_imem_en;
	
  sc_signal< sc_bv<W_ALUCTRL>		> bus_aluctrl;
	
  sc_signal< sc_bv<W_BRANCHFLAG>	> bus_branch;


  // Signals needed for pipelining
  // Instruction fecth -> Instruction decode
  sc_signal< sc_bv<DWORD>			> bus_if_pc; 
  sc_signal< sc_bv<DWORD>			> bus_if_instr; 

  // Instruction decode -> Execution
  sc_signal< sc_bv<DWORD>			> bus_id_pc; 
  sc_signal< sc_bv<DWORD> 		> bus_id_data_reg1; 
  sc_signal< sc_bv<DWORD>			> bus_id_data_reg2; 
  sc_signal< sc_bv<DWORD>			> bus_id_immediate; 
  sc_signal< sc_bv<DWORD> 		> bus_id_instr_25_0; 
  sc_signal< sc_bv<AWORDREG> 		> bus_id_instr_20_16; 
  sc_signal< sc_bv<AWORDREG> 		> bus_id_instr_15_11; 
  sc_signal< sc_bv<6> 			> bus_id_instr_5_0; 
  sc_signal< sc_bv<5> 			> bus_id_instr_10_6; 
  sc_signal< sc_bv<W_ALUSRC> 		> bus_id_ctrl_ex_alusrc; 
  sc_signal< sc_bv<W_ALUOP> 		> bus_id_ctrl_ex_aluop; 
  sc_signal< sc_bv<W_REGDST>		> bus_id_ctrl_ex_regdst; 
  sc_signal< sc_bv<W_REGVAL>		> bus_id_ctrl_ex_regvalue; 
  sc_signal< sc_bv<W_TARGET>		> bus_id_ctrl_ex_target; 
  sc_signal< sc_bv<W_BRANCHOP> 	> bus_id_ctrl_mem_branch; 
  sc_signal< sc_bv<W_MEMWRITE> 	> bus_id_ctrl_mem_memwrite; 
  sc_signal< sc_bv<W_MEMREAD>		> bus_id_ctrl_mem_memread; 
  sc_signal< sc_bv<W_REGWRITE> 	> bus_id_ctrl_wb_regwrite; 
  sc_signal< sc_bv<W_MEMTOREG> 	> bus_id_ctrl_wb_memtoreg; 

  // Execution -> Memory stage
  sc_signal< sc_bv<AWORDREG> > bus_ex_regdst_addr; 
  sc_signal< sc_bv<DWORD> > bus_ex_alu_result; 
  sc_signal< sc_bv<W_REGWRITE> > bus_ex_ctrl_wb_regwrite; 
  sc_signal< sc_bv<W_MEMTOREG> > bus_ex_ctrl_wb_memtoreg; 

  // Memory stage -> Write back stage
  sc_signal< sc_bv<DWORD>			> bus_mem_dmem_data; 
  sc_signal< sc_bv<DWORD>			> bus_mem_alu_result; 
  sc_signal< sc_bv<AWORDREG> 		> bus_mem_regdst_addr; 
  sc_signal< sc_bv<W_REGWRITE> 	> bus_mem_ctrl_wb_regwrite; 
  sc_signal< sc_bv<W_MEMTOREG> 	> bus_mem_ctrl_wb_memtoreg; 
	
  // Hazard detection unit
  sc_signal< sc_bv<W_PCWRITEFLAG>	> bus_hazard_pcwrite; 
  sc_signal< sc_bv<W_IFIDWRITEFLAG> > bus_hazard_ifidwrite; 
  sc_signal< sc_bv<W_HAZARDFLAG>	> bus_hazard_hazard; 
	
  sc_signal< sc_bv<W_REGDST>		> bus_ctrl2hazard_regdst;
  sc_signal< sc_bv<W_REGVAL>		> bus_ctrl2hazard_regvalue;
  sc_signal< sc_bv<W_TARGET>		> bus_ctrl2hazard_target;
  sc_signal< sc_bv<W_BRANCHOP> 	> bus_ctrl2hazard_branch;
  sc_signal< sc_bv<W_MEMREAD>		> bus_ctrl2hazard_memread;
  sc_signal< sc_bv<W_MEMTOREG>	> bus_ctrl2hazard_memtoreg;
  sc_signal< sc_bv<W_ALUOP> 		> bus_ctrl2hazard_aluop;
  sc_signal< sc_bv<W_MEMWRITE>	> bus_ctrl2hazard_memwrite;
  sc_signal< sc_bv<W_ALUSRC>		> bus_ctrl2hazard_alusrc;
  sc_signal< sc_bv<W_REGWRITE>	> bus_ctrl2hazard_regwrite;
  
  /*
   *	MODULES
   */
#ifndef VERILOG
  // Pipeline registers
  // Instruction fecth -> Instruction decode
  REGISTER<DWORD>		*if_pc;
  REGISTER<DWORD>		*if_instr;

  // Instruction decode -> Execution
  REGISTER<DWORD>		*id_pc;
  REGISTER<DWORD>		*id_data_reg1;
  REGISTER<DWORD>		*id_data_reg2;
  REGISTER<DWORD>		*id_immediate;
  REGISTER<DWORD>		*id_instr_25_0;
  REGISTER<AWORDREG>	*id_instr_20_16;
  REGISTER<AWORDREG>	*id_instr_15_11;
  REGISTER<6>			*id_instr_5_0;
  REGISTER<5>			*id_instr_10_6;
  REGISTER<W_ALUSRC>	*id_ctrl_ex_alusrc;
  REGISTER<W_ALUOP>	*id_ctrl_ex_aluop;
  REGISTER<W_REGDST>	*id_ctrl_ex_regdst;
  REGISTER<W_REGVAL>	*id_ctrl_ex_regvalue;
  REGISTER<W_TARGET>	*id_ctrl_ex_target;
  REGISTER<W_BRANCHOP> *id_ctrl_mem_branch;
  REGISTER<W_MEMWRITE> *id_ctrl_mem_memwrite;
  REGISTER<W_MEMREAD>	*id_ctrl_mem_memread;
  REGISTER<W_REGWRITE> *id_ctrl_wb_regwrite;
  REGISTER<W_MEMTOREG> *id_ctrl_wb_memtoreg;

  // Execution -> Memory stage
  REGISTER<AWORDREG>	*ex_regdst_addr;
  REGISTER<DWORD>		*ex_alu_result;
  REGISTER<W_REGWRITE> *ex_ctrl_wb_regwrite;
  REGISTER<W_MEMTOREG> *ex_ctrl_wb_memtoreg;

  // Memory stage -> Write back stage
  REGISTER<DWORD>		*mem_dmem_data;
  REGISTER<DWORD>		*mem_alu_result;
  REGISTER<AWORDREG>	*mem_regdst_addr;
  REGISTER<W_REGWRITE> *mem_ctrl_wb_regwrite;
  REGISTER<W_MEMTOREG> *mem_ctrl_wb_memtoreg;


  // program counter
  REGISTER<DWORD>	*pc;
#else // VERILOG

  // Pipeline registers
  // Instruction fecth - Instruction decode
  REGISTER_DWORD		*if_pc;
  REGISTER_DWORD		*if_instr;

  // Instruction decode - Execution
  REGISTER_DWORD		*id_pc;
  REGISTER_DWORD		*id_data_reg1;
  REGISTER_DWORD		*id_data_reg2;
  REGISTER_DWORD		*id_immediate;
  REGISTER_DWORD		*id_instr_25_0;
  REGISTER_AWORDREG	*id_instr_20_16;
  REGISTER_AWORDREG	*id_instr_15_11;
  REGISTER_6			*id_instr_5_0;
  REGISTER_5			*id_instr_10_6;
  REGISTER_W_ALUSRC	*id_ctrl_ex_alusrc;
  REGISTER_W_ALUOP	*id_ctrl_ex_aluop;
  REGISTER_W_REGDST	*id_ctrl_ex_regdst;
  REGISTER_W_REGVAL	*id_ctrl_ex_regvalue;
  REGISTER_W_TARGET	*id_ctrl_ex_target;
  REGISTER_W_BRANCHOP *id_ctrl_mem_branch;
  REGISTER_W_MEMWRITE *id_ctrl_mem_memwrite;
  REGISTER_W_MEMREAD	*id_ctrl_mem_memread;
  REGISTER_W_REGWRITE *id_ctrl_wb_regwrite;
  REGISTER_W_MEMTOREG *id_ctrl_wb_memtoreg;

  // Execution - Memory stage
  REGISTER_AWORDREG	*ex_regdst_addr;
  REGISTER_DWORD		*ex_alu_result;
  REGISTER_W_REGWRITE *ex_ctrl_wb_regwrite;
  REGISTER_W_MEMTOREG *ex_ctrl_wb_memtoreg;

  // Memory stage - Write back stage
  REGISTER_DWORD		*mem_dmem_data;
  REGISTER_DWORD		*mem_alu_result;
  REGISTER_AWORDREG	*mem_regdst_addr;
  REGISTER_W_REGWRITE *mem_ctrl_wb_regwrite;
  REGISTER_W_MEMTOREG *mem_ctrl_wb_memtoreg;
  
  // program counter
  REGISTER_DWORD	*pc;
#endif
  
  // Hazard handling
  HAZARD				*hazard;
  HAZARD_CTRL			*hazard_ctrl;
					
  // Branch handling
  BRANCH_CTRL		*branch_ctrl;
	 
  // Modules used for computation
							
  ADD				*add1;
  ADD				*add2;
	
#ifdef ICACHE
  DATA_CACHE       *imem;

  sc_out< sc_bv<32> > icache_addr, icache_din;
  sc_in< sc_bv<32> > icache_dout;
  sc_out< bool > icache_ww, icache_wb, icache_r;
  sc_in< bool > icache_rdy;
  
  sc_signal< sc_bv<W_MEMWRITE> > c0_imem_w;
  sc_signal< sc_bv<W_MEMREAD> > c1_imem_r;
  sc_signal< sc_bv<DWORD> > c0_imem_din;
  
#else
  BROM16K				*imem;

  sc_out<sc_int<32> > romDO;
  sc_in<sc_uint<32> > romADDR;
  sc_in<sc_int<32> > romDI;
  sc_in<bool> romEN;
  sc_in<bool> romCLK;
  sc_in<bool> romWE;
  sc_in<bool> romRST;

#endif
  
#ifdef DCACHE
  
  DATA_CACHE		*dmem;
  
  sc_out< sc_bv<32> > dcache_addr, dcache_din;
  sc_in< sc_bv<32> > dcache_dout;
  sc_out< bool > dcache_ww, dcache_wb, dcache_r;
  sc_in< bool > dcache_rdy;
  
#else
  
  BRAM16K				*dmem;

  sc_out<sc_int<32> > ramDO;
  sc_in<sc_uint<32> > ramADDR;
  sc_in<sc_int<32> > ramDI;
  sc_in<bool> ramEN;
  sc_in<bool> ramCLK;
  sc_in<bool> ramWE;
  sc_in<bool> ramRST;

#endif
	  
  
  REGFILE16			*registers;
	
  ALU				*alu;
  ALUCTRL			*aluctrl;
	
  IMM2WORD		    *imm2word;

  SIGNEXTEND_BYTE	*signextendbyte;
	
  SHIFTLEFT		*shiftleft;
  SHIFTLEFT		*shiftleft_jmp;
	
  CTRL			*ctrl;
	
  DECODER			*decoder;

  sc_signal< sc_bv<AWORDREG> 		> bus_decoder_nb_instr_25_21;
  sc_signal< sc_bv<AWORDREG> 		> bus_decoder_nb_instr_20_16;
  DECODER_NBUF      *decoder_nb;
  MUX2 *mux7;
  sc_signal< sc_bv<DWORD> > bus_mux7;


  MUX2			*mux1;
  MUX2			*mux2;
  MUX3			*mux3;
  MUX3_AWORDREG	*mux4;
  MUX3			*mux5;
  MUX2			*mux6;

  CLKDIST       *clkdist;

  
  // memory-mapped-device infrostructure
  MEMDEV *memdev;

  sc_out< sc_bv<DWORD> > dev_dout;
  sc_in< sc_bv<DWORD> > dev_din;
  sc_out< bool > dev_r, dev_w;
  sc_in< bool > dev_rdyr, dev_rdyw;
  sc_out< bool > dev_wdata, dev_waddr;
  sc_out<bool> dev_send_eop;
  sc_in<bool> dev_rcv_eop;
  
  
  sc_signal< sc_bv<DWORD> > bus_ram_din, bus_ram_addr, bus_ram_dout;
  sc_signal< bool > bus_ram_wait;
  sc_signal< sc_bv<W_MEMREAD> > bus_ram_r;
  sc_signal< sc_bv<W_MEMWRITE> > bus_ram_w;

  sc_signal< bool > bus_dmem_wait;
  sc_signal< bool > bus_imem_wait;

  // constants
  sc_signal< sc_bv<1> > GND, VCC;

#ifdef USEXRAM
  XRAM *xram;
  SIGNAL_DBG *signal_dbg;
  
  sc_signal< sc_int<32> > xDI;
  sc_out< sc_int<32> > xDO;
  sc_in< sc_uint<32> > xADDR;
  sc_in< bool > xCLK, xWE;
#endif
  
  SC_CTOR(mMIPS){

	GND = 0;
	VCC = 1;
#ifndef VERILOG
	
	if_pc = new REGISTER<DWORD>("IF_pc"); 
	if_instr = new REGISTER<DWORD>("IF_instr"); 
	id_pc = new REGISTER<DWORD>("ID_pc"); 
	id_data_reg1 = new REGISTER<DWORD>("ID_data_reg1"); 
	id_data_reg2 = new REGISTER<DWORD>("ID_data_reg2"); 
	id_immediate = new REGISTER<DWORD>("ID_immediate"); 
	id_instr_25_0 = new REGISTER<DWORD>("ID_instr_25_0"); 
	id_instr_20_16 = new REGISTER<AWORDREG>("ID_instr_20_16"); 
	id_instr_15_11 = new REGISTER<AWORDREG>("ID_instr_15_11"); 
	id_instr_5_0 = new REGISTER<6>("ID_instr_5_0"); 
	id_instr_10_6 = new REGISTER<5>("ID_instr_10_6"); 
	id_ctrl_ex_alusrc = new REGISTER<W_ALUSRC>("ID_ctrl_ex_alusrc"); 
	id_ctrl_ex_aluop = new REGISTER<W_ALUOP>("ID_ctrl_ex_aluop"); 
	id_ctrl_ex_regdst = new REGISTER<W_REGDST>("ID_ctrl_ex_regdst"); 
	id_ctrl_ex_regvalue = new REGISTER<W_REGVAL>("ID_ctrl_ex_regvalue"); 
	id_ctrl_ex_target = new REGISTER<W_TARGET>("ID_ctrl_ex_target"); 
	id_ctrl_mem_branch = new REGISTER<W_BRANCHOP>("ID_ctrl_mem_branch"); 
	id_ctrl_mem_memwrite = new REGISTER<W_MEMWRITE>("ID_ctrl_mem_memwrite"); 
	id_ctrl_mem_memread = new REGISTER<W_MEMREAD>("ID_ctrl_mem_memread"); 
	id_ctrl_wb_regwrite = new REGISTER<W_REGWRITE>("ID_ctrl_wb_regwrite"); 
	id_ctrl_wb_memtoreg = new REGISTER<W_MEMTOREG>("ID_ctrl_wb_memtoreg"); 
	ex_regdst_addr = new REGISTER<AWORDREG>("EX_regdst_addr"); 
	ex_alu_result = new REGISTER<DWORD>("EX_alu_result"); 
	ex_ctrl_wb_regwrite = new REGISTER<W_REGWRITE>("EX_ctrl_wb_regwrite"); 
	ex_ctrl_wb_memtoreg = new REGISTER<W_MEMTOREG>("EX_ctrl_wb_memtoreg"); 
	mem_dmem_data = new REGISTER<DWORD>("MEM_dmem_data"); 
	mem_alu_result = new REGISTER<DWORD>("MEM_alu_result"); 
	mem_regdst_addr = new REGISTER<AWORDREG>("MEM_regdst_addr"); 
	mem_ctrl_wb_regwrite = new REGISTER<W_REGWRITE>("MEM_ctrl_wb_regwrite"); 
	mem_ctrl_wb_memtoreg = new REGISTER<W_MEMTOREG>("MEM_ctrl_wb_memtoreg"); 

	pc = new REGISTER<DWORD>("pc");					
#else // VERILOG

	if_pc = new REGISTER_DWORD("IF_pc"); 
	if_instr = new REGISTER_DWORD("IF_instr"); 
	id_pc = new REGISTER_DWORD("ID_pc"); 
	id_data_reg1 = new REGISTER_DWORD("ID_data_reg1"); 
	id_data_reg2 = new REGISTER_DWORD("ID_data_reg2"); 
	id_immediate = new REGISTER_DWORD("ID_immediate"); 
	id_instr_25_0 = new REGISTER_DWORD("ID_instr_25_0"); 
	id_instr_20_16 = new REGISTER_AWORDREG("ID_instr_20_16"); 
	id_instr_15_11 = new REGISTER_AWORDREG("ID_instr_15_11"); 
	id_instr_5_0 = new REGISTER_6("ID_instr_5_0"); 
	id_instr_10_6 = new REGISTER_5("ID_instr_10_6"); 
	id_ctrl_ex_alusrc = new REGISTER_W_ALUSRC("ID_ctrl_ex_alusrc"); 
	id_ctrl_ex_aluop = new REGISTER_W_ALUOP("ID_ctrl_ex_aluop"); 
	id_ctrl_ex_regdst = new REGISTER_W_REGDST("ID_ctrl_ex_regdst"); 
	id_ctrl_ex_regvalue = new REGISTER_W_REGVAL("ID_ctrl_ex_regvalue"); 
	id_ctrl_ex_target = new REGISTER_W_TARGET("ID_ctrl_ex_target"); 
	id_ctrl_mem_branch = new REGISTER_W_BRANCHOP("ID_ctrl_mem_branch"); 
	id_ctrl_mem_memwrite = new REGISTER_W_MEMWRITE("ID_ctrl_mem_memwrite"); 
	id_ctrl_mem_memread = new REGISTER_W_MEMREAD("ID_ctrl_mem_memread"); 
	id_ctrl_wb_regwrite = new REGISTER_W_REGWRITE("ID_ctrl_wb_regwrite"); 
	id_ctrl_wb_memtoreg = new REGISTER_W_MEMTOREG("ID_ctrl_wb_memtoreg"); 
	ex_regdst_addr = new REGISTER_AWORDREG("EX_regdst_addr"); 
	ex_alu_result = new REGISTER_DWORD("EX_alu_result"); 
	ex_ctrl_wb_regwrite = new REGISTER_W_REGWRITE("EX_ctrl_wb_regwrite"); 
	ex_ctrl_wb_memtoreg = new REGISTER_W_MEMTOREG("EX_ctrl_wb_memtoreg"); 
	mem_dmem_data = new REGISTER_DWORD("MEM_dmem_data"); 
	mem_alu_result = new REGISTER_DWORD("MEM_alu_result"); 
	mem_regdst_addr = new REGISTER_AWORDREG("MEM_regdst_addr"); 
	mem_ctrl_wb_regwrite = new REGISTER_W_REGWRITE("MEM_ctrl_wb_regwrite"); 
	mem_ctrl_wb_memtoreg = new REGISTER_W_MEMTOREG("MEM_ctrl_wb_memtoreg"); 

	pc = new REGISTER_DWORD("pc");						

#endif
	
	hazard = new HAZARD("hazard"); 			
	hazard_ctrl = new HAZARD_CTRL("hazard_ctrl"); 
	branch_ctrl = new BRANCH_CTRL("branch_ctrl");
	
	add1 = new ADD("add1");
	add2 = new ADD("add2");	
#ifdef ICACHE
	imem = new DATA_CACHE("instruction_memory");

	c0_imem_w = 0;
	c1_imem_r = 1;
	c0_imem_din = 0;
	
	imem->mem_addr(icache_addr);
	imem->mem_din(icache_din);
	imem->mem_dout(icache_dout);
	imem->mem_ww(icache_ww);
	imem->mem_wb(icache_wb);
	imem->mem_r(icache_r);
	imem->mem_rdy(icache_rdy);
#else	
	imem = new BROM16K("instruction_memory");
#endif
	
#ifdef DCACHE
	dmem = new DATA_CACHE("data_memory");

	dmem->mem_addr(dcache_addr);
	dmem->mem_din(dcache_din);
	dmem->mem_dout(dcache_dout);
	dmem->mem_ww(dcache_ww);
	dmem->mem_wb(dcache_wb);
	dmem->mem_r(dcache_r);