_network8x8.cpp

国外开源的一个片上网络系统的源代码

	dp_x5y0.req_in(x5y0req_dp);

	dp_x5y1.data_in(x5y1dout);
	dp_x5y1.data_out(x5y1din);
	dp_x5y1.req_out(x5y1req_net);
	dp_x5y1.ack_in(x5y1ack_net);
	dp_x5y1.ack_out(x5y1ack_dp);
	dp_x5y1.req_in(x5y1req_dp);

	dp_x5y2.data_in(x5y2dout);
	dp_x5y2.data_out(x5y2din);
	dp_x5y2.req_out(x5y2req_net);
	dp_x5y2.ack_in(x5y2ack_net);
	dp_x5y2.ack_out(x5y2ack_dp);
	dp_x5y2.req_in(x5y2req_dp);

	dp_x5y3.data_in(x5y3dout);
	dp_x5y3.data_out(x5y3din);
	dp_x5y3.req_out(x5y3req_net);
	dp_x5y3.ack_in(x5y3ack_net);
	dp_x5y3.ack_out(x5y3ack_dp);
	dp_x5y3.req_in(x5y3req_dp);

	dp_x5y4.data_in(x5y4dout);
	dp_x5y4.data_out(x5y4din);
	dp_x5y4.req_out(x5y4req_net);
	dp_x5y4.ack_in(x5y4ack_net);
	dp_x5y4.ack_out(x5y4ack_dp);
	dp_x5y4.req_in(x5y4req_dp);

	dp_x5y5.data_in(x5y5dout);
	dp_x5y5.data_out(x5y5din);
	dp_x5y5.req_out(x5y5req_net);
	dp_x5y5.ack_in(x5y5ack_net);
	dp_x5y5.ack_out(x5y5ack_dp);
	dp_x5y5.req_in(x5y5req_dp);

	dp_x5y6.data_in(x5y6dout);
	dp_x5y6.data_out(x5y6din);
	dp_x5y6.req_out(x5y6req_net);
	dp_x5y6.ack_in(x5y6ack_net);
	dp_x5y6.ack_out(x5y6ack_dp);
	dp_x5y6.req_in(x5y6req_dp);

	dp_x5y7.data_in(x5y7dout);
	dp_x5y7.data_out(x5y7din);
	dp_x5y7.req_out(x5y7req_net);
	dp_x5y7.ack_in(x5y7ack_net);
	dp_x5y7.ack_out(x5y7ack_dp);
	dp_x5y7.req_in(x5y7req_dp);

	dp_x6y0.data_in(x6y0dout);
	dp_x6y0.data_out(x6y0din);
	dp_x6y0.req_out(x6y0req_net);
	dp_x6y0.ack_in(x6y0ack_net);
	dp_x6y0.ack_out(x6y0ack_dp);
	dp_x6y0.req_in(x6y0req_dp);

	dp_x6y1.data_in(x6y1dout);
	dp_x6y1.data_out(x6y1din);
	dp_x6y1.req_out(x6y1req_net);
	dp_x6y1.ack_in(x6y1ack_net);
	dp_x6y1.ack_out(x6y1ack_dp);
	dp_x6y1.req_in(x6y1req_dp);

	dp_x6y2.data_in(x6y2dout);
	dp_x6y2.data_out(x6y2din);
	dp_x6y2.req_out(x6y2req_net);
	dp_x6y2.ack_in(x6y2ack_net);
	dp_x6y2.ack_out(x6y2ack_dp);
	dp_x6y2.req_in(x6y2req_dp);

	dp_x6y3.data_in(x6y3dout);
	dp_x6y3.data_out(x6y3din);
	dp_x6y3.req_out(x6y3req_net);
	dp_x6y3.ack_in(x6y3ack_net);
	dp_x6y3.ack_out(x6y3ack_dp);
	dp_x6y3.req_in(x6y3req_dp);

	dp_x6y4.data_in(x6y4dout);
	dp_x6y4.data_out(x6y4din);
	dp_x6y4.req_out(x6y4req_net);
	dp_x6y4.ack_in(x6y4ack_net);
	dp_x6y4.ack_out(x6y4ack_dp);
	dp_x6y4.req_in(x6y4req_dp);

	dp_x6y5.data_in(x6y5dout);
	dp_x6y5.data_out(x6y5din);
	dp_x6y5.req_out(x6y5req_net);
	dp_x6y5.ack_in(x6y5ack_net);
	dp_x6y5.ack_out(x6y5ack_dp);
	dp_x6y5.req_in(x6y5req_dp);

	dp_x6y6.data_in(x6y6dout);
	dp_x6y6.data_out(x6y6din);
	dp_x6y6.req_out(x6y6req_net);
	dp_x6y6.ack_in(x6y6ack_net);
	dp_x6y6.ack_out(x6y6ack_dp);
	dp_x6y6.req_in(x6y6req_dp);

	dp_x6y7.data_in(x6y7dout);
	dp_x6y7.data_out(x6y7din);
	dp_x6y7.req_out(x6y7req_net);
	dp_x6y7.ack_in(x6y7ack_net);
	dp_x6y7.ack_out(x6y7ack_dp);
	dp_x6y7.req_in(x6y7req_dp);

	dp_x7y0.data_in(x7y0dout);
	dp_x7y0.data_out(x7y0din);
	dp_x7y0.req_out(x7y0req_net);
	dp_x7y0.ack_in(x7y0ack_net);
	dp_x7y0.ack_out(x7y0ack_dp);
	dp_x7y0.req_in(x7y0req_dp);

	dp_x7y1.data_in(x7y1dout);
	dp_x7y1.data_out(x7y1din);
	dp_x7y1.req_out(x7y1req_net);
	dp_x7y1.ack_in(x7y1ack_net);
	dp_x7y1.ack_out(x7y1ack_dp);
	dp_x7y1.req_in(x7y1req_dp);

	dp_x7y2.data_in(x7y2dout);
	dp_x7y2.data_out(x7y2din);
	dp_x7y2.req_out(x7y2req_net);
	dp_x7y2.ack_in(x7y2ack_net);
	dp_x7y2.ack_out(x7y2ack_dp);
	dp_x7y2.req_in(x7y2req_dp);

	dp_x7y3.data_in(x7y3dout);
	dp_x7y3.data_out(x7y3din);
	dp_x7y3.req_out(x7y3req_net);
	dp_x7y3.ack_in(x7y3ack_net);
	dp_x7y3.ack_out(x7y3ack_dp);
	dp_x7y3.req_in(x7y3req_dp);

	dp_x7y4.data_in(x7y4dout);
	dp_x7y4.data_out(x7y4din);
	dp_x7y4.req_out(x7y4req_net);
	dp_x7y4.ack_in(x7y4ack_net);
	dp_x7y4.ack_out(x7y4ack_dp);
	dp_x7y4.req_in(x7y4req_dp);

	dp_x7y5.data_in(x7y5dout);
	dp_x7y5.data_out(x7y5din);
	dp_x7y5.req_out(x7y5req_net);
	dp_x7y5.ack_in(x7y5ack_net);
	dp_x7y5.ack_out(x7y5ack_dp);
	dp_x7y5.req_in(x7y5req_dp);

	dp_x7y6.data_in(x7y6dout);
	dp_x7y6.data_out(x7y6din);
	dp_x7y6.req_out(x7y6req_net);
	dp_x7y6.ack_in(x7y6ack_net);
	dp_x7y6.ack_out(x7y6ack_dp);
	dp_x7y6.req_in(x7y6req_dp);

	dp_x7y7.data_in(x7y7dout);
	dp_x7y7.data_out(x7y7din);
	dp_x7y7.req_out(x7y7req_net);
	dp_x7y7.ack_in(x7y7ack_net);
	dp_x7y7.ack_out(x7y7ack_dp);
	dp_x7y7.req_in(x7y7req_dp);

	sc_signal<sc_uint<32> > dp_x0y0_ramADDR;
	sc_signal<sc_int<32> > dp_x0y0_ramDI;
	sc_signal<sc_int<32> > dp_x0y0_ramDO;
	sc_signal<bool> dp_x0y0_ramEN;
	sc_signal<bool> dp_x0y0_ramCLK;
	sc_signal<bool> dp_x0y0_ramWE;
	sc_signal<bool> dp_x0y0_ramRST;
	sc_signal<sc_uint<32> > dp_x0y0_romADDR;
	sc_signal<sc_int<32> > dp_x0y0_romDI;
	sc_signal<sc_int<32> > dp_x0y0_romDO;
	sc_signal<bool> dp_x0y0_romEN;
	sc_signal<bool> dp_x0y0_romCLK;
	sc_signal<bool> dp_x0y0_romWE;
	sc_signal<bool> dp_x0y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y0_xDO;
	sc_signal< sc_uint<32> > dp_x0y0_xADDR;
	sc_signal< bool > dp_x0y0_xCLK, dp_x0y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y1_ramADDR;
	sc_signal<sc_int<32> > dp_x0y1_ramDI;
	sc_signal<sc_int<32> > dp_x0y1_ramDO;
	sc_signal<bool> dp_x0y1_ramEN;
	sc_signal<bool> dp_x0y1_ramCLK;
	sc_signal<bool> dp_x0y1_ramWE;
	sc_signal<bool> dp_x0y1_ramRST;
	sc_signal<sc_uint<32> > dp_x0y1_romADDR;
	sc_signal<sc_int<32> > dp_x0y1_romDI;
	sc_signal<sc_int<32> > dp_x0y1_romDO;
	sc_signal<bool> dp_x0y1_romEN;
	sc_signal<bool> dp_x0y1_romCLK;
	sc_signal<bool> dp_x0y1_romWE;
	sc_signal<bool> dp_x0y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y1_xDO;
	sc_signal< sc_uint<32> > dp_x0y1_xADDR;
	sc_signal< bool > dp_x0y1_xCLK, dp_x0y1_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y2_ramADDR;
	sc_signal<sc_int<32> > dp_x0y2_ramDI;
	sc_signal<sc_int<32> > dp_x0y2_ramDO;
	sc_signal<bool> dp_x0y2_ramEN;
	sc_signal<bool> dp_x0y2_ramCLK;
	sc_signal<bool> dp_x0y2_ramWE;
	sc_signal<bool> dp_x0y2_ramRST;
	sc_signal<sc_uint<32> > dp_x0y2_romADDR;
	sc_signal<sc_int<32> > dp_x0y2_romDI;
	sc_signal<sc_int<32> > dp_x0y2_romDO;
	sc_signal<bool> dp_x0y2_romEN;
	sc_signal<bool> dp_x0y2_romCLK;
	sc_signal<bool> dp_x0y2_romWE;
	sc_signal<bool> dp_x0y2_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y2_xDO;
	sc_signal< sc_uint<32> > dp_x0y2_xADDR;
	sc_signal< bool > dp_x0y2_xCLK, dp_x0y2_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y3_ramADDR;
	sc_signal<sc_int<32> > dp_x0y3_ramDI;
	sc_signal<sc_int<32> > dp_x0y3_ramDO;
	sc_signal<bool> dp_x0y3_ramEN;
	sc_signal<bool> dp_x0y3_ramCLK;
	sc_signal<bool> dp_x0y3_ramWE;
	sc_signal<bool> dp_x0y3_ramRST;
	sc_signal<sc_uint<32> > dp_x0y3_romADDR;
	sc_signal<sc_int<32> > dp_x0y3_romDI;
	sc_signal<sc_int<32> > dp_x0y3_romDO;
	sc_signal<bool> dp_x0y3_romEN;
	sc_signal<bool> dp_x0y3_romCLK;
	sc_signal<bool> dp_x0y3_romWE;
	sc_signal<bool> dp_x0y3_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y3_xDO;
	sc_signal< sc_uint<32> > dp_x0y3_xADDR;
	sc_signal< bool > dp_x0y3_xCLK, dp_x0y3_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y4_ramADDR;
	sc_signal<sc_int<32> > dp_x0y4_ramDI;
	sc_signal<sc_int<32> > dp_x0y4_ramDO;
	sc_signal<bool> dp_x0y4_ramEN;
	sc_signal<bool> dp_x0y4_ramCLK;
	sc_signal<bool> dp_x0y4_ramWE;
	sc_signal<bool> dp_x0y4_ramRST;
	sc_signal<sc_uint<32> > dp_x0y4_romADDR;
	sc_signal<sc_int<32> > dp_x0y4_romDI;
	sc_signal<sc_int<32> > dp_x0y4_romDO;
	sc_signal<bool> dp_x0y4_romEN;
	sc_signal<bool> dp_x0y4_romCLK;
	sc_signal<bool> dp_x0y4_romWE;
	sc_signal<bool> dp_x0y4_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y4_xDO;
	sc_signal< sc_uint<32> > dp_x0y4_xADDR;
	sc_signal< bool > dp_x0y4_xCLK, dp_x0y4_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y5_ramADDR;
	sc_signal<sc_int<32> > dp_x0y5_ramDI;
	sc_signal<sc_int<32> > dp_x0y5_ramDO;
	sc_signal<bool> dp_x0y5_ramEN;
	sc_signal<bool> dp_x0y5_ramCLK;
	sc_signal<bool> dp_x0y5_ramWE;
	sc_signal<bool> dp_x0y5_ramRST;
	sc_signal<sc_uint<32> > dp_x0y5_romADDR;
	sc_signal<sc_int<32> > dp_x0y5_romDI;
	sc_signal<sc_int<32> > dp_x0y5_romDO;
	sc_signal<bool> dp_x0y5_romEN;
	sc_signal<bool> dp_x0y5_romCLK;
	sc_signal<bool> dp_x0y5_romWE;
	sc_signal<bool> dp_x0y5_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y5_xDO;
	sc_signal< sc_uint<32> > dp_x0y5_xADDR;
	sc_signal< bool > dp_x0y5_xCLK, dp_x0y5_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y6_ramADDR;
	sc_signal<sc_int<32> > dp_x0y6_ramDI;
	sc_signal<sc_int<32> > dp_x0y6_ramDO;
	sc_signal<bool> dp_x0y6_ramEN;
	sc_signal<bool> dp_x0y6_ramCLK;
	sc_signal<bool> dp_x0y6_ramWE;
	sc_signal<bool> dp_x0y6_ramRST;
	sc_signal<sc_uint<32> > dp_x0y6_romADDR;
	sc_signal<sc_int<32> > dp_x0y6_romDI;
	sc_signal<sc_int<32> > dp_x0y6_romDO;
	sc_signal<bool> dp_x0y6_romEN;
	sc_signal<bool> dp_x0y6_romCLK;
	sc_signal<bool> dp_x0y6_romWE;
	sc_signal<bool> dp_x0y6_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y6_xDO;
	sc_signal< sc_uint<32> > dp_x0y6_xADDR;
	sc_signal< bool > dp_x0y6_xCLK, dp_x0y6_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y7_ramADDR;
	sc_signal<sc_int<32> > dp_x0y7_ramDI;
	sc_signal<sc_int<32> > dp_x0y7_ramDO;
	sc_signal<bool> dp_x0y7_ramEN;
	sc_signal<bool> dp_x0y7_ramCLK;
	sc_signal<bool> dp_x0y7_ramWE;
	sc_signal<bool> dp_x0y7_ramRST;
	sc_signal<sc_uint<32> > dp_x0y7_romADDR;
	sc_signal<sc_int<32> > dp_x0y7_romDI;
	sc_signal<sc_int<32> > dp_x0y7_romDO;
	sc_signal<bool> dp_x0y7_romEN;
	sc_signal<bool> dp_x0y7_romCLK;
	sc_signal<bool> dp_x0y7_romWE;
	sc_signal<bool> dp_x0y7_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y7_xDO;
	sc_signal< sc_uint<32> > dp_x0y7_xADDR;
	sc_signal< bool > dp_x0y7_xCLK, dp_x0y7_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y0_ramADDR;
	sc_signal<sc_int<32> > dp_x1y0_ramDI;
	sc_signal<sc_int<32> > dp_x1y0_ramDO;
	sc_signal<bool> dp_x1y0_ramEN;
	sc_signal<bool> dp_x1y0_ramCLK;
	sc_signal<bool> dp_x1y0_ramWE;
	sc_signal<bool> dp_x1y0_ramRST;
	sc_signal<sc_uint<32> > dp_x1y0_romADDR;
	sc_signal<sc_int<32> > dp_x1y0_romDI;
	sc_signal<sc_int<32> > dp_x1y0_romDO;
	sc_signal<bool> dp_x1y0_romEN;
	sc_signal<bool> dp_x1y0_romCLK;
	sc_signal<bool> dp_x1y0_romWE;
	sc_signal<bool> dp_x1y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y0_xDO;
	sc_signal< sc_uint<32> > dp_x1y0_xADDR;
	sc_signal< bool > dp_x1y0_xCLK, dp_x1y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y1_ramADDR;
	sc_signal<sc_int<32> > dp_x1y1_ramDI;
	sc_signal<sc_int<32> > dp_x1y1_ramDO;
	sc_signal<bool> dp_x1y1_ramEN;
	sc_signal<bool> dp_x1y1_ramCLK;
	sc_signal<bool> dp_x1y1_ramWE;
	sc_signal<bool> dp_x1y1_ramRST;
	sc_signal<sc_uint<32> > dp_x1y1_romADDR;
	sc_signal<sc_int<32> > dp_x1y1_romDI;
	sc_signal<sc_int<32> > dp_x1y1_romDO;
	sc_signal<bool> dp_x1y1_romEN;
	sc_signal<bool> dp_x1y1_romCLK;
	sc_signal<bool> dp_x1y1_romWE;
	sc_signal<bool> dp_x1y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y1_xDO;
	sc_signal< sc_uint<32> > dp_x1y1_xADDR;
	sc_signal< bool > dp_x1y1_xCLK, dp_x1y1_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y2_ramADDR;
	sc_signal<sc_int<32> > dp_x1y2_ramDI;
	sc_signal<sc_int<32> > dp_x1y2_ramDO;
	sc_signal<bool> dp_x1y2_ramEN;
	sc_signal<bool> dp_x1y2_ramCLK;
	sc_signal<bool> dp_x1y2_ramWE;
	sc_signal<bool> dp_x1y2_ramRST;
	sc_signal<sc_uint<32> > dp_x1y2_romADDR;
	sc_signal<sc_int<32> > dp_x1y2_romDI;
	sc_signal<sc_int<32> > dp_x1y2_romDO;
	sc_signal<bool> dp_x1y2_romEN;
	sc_signal<bool> dp_x1y2_romCLK;
	sc_signal<bool> dp_x1y2_romWE;
	sc_signal<bool> dp_x1y2_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y2_xDO;
	sc_signal< sc_uint<32> > dp_x1y2_xADDR;
	sc_signal< bool > dp_x1y2_xCLK, dp_x1y2_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y3_ramADDR;
	sc_signal<sc_int<32> > dp_x1y3_ramDI;
	sc_signal<sc_int<32> > dp_x1y3_ramDO;
	sc_signal<bool> dp_x1y3_ramEN;
	sc_signal<bool> dp_x1y3_ramCLK;
	sc_signal<bool> dp_x1y3_ramWE;
	sc_signal<bool> dp_x1y3_ramRST;
	sc_signal<sc_uint<32> > dp_x1y3_romADDR;
	sc_signal<sc_int<32> > dp_x1y3_romDI;
	sc_signal<sc_int<32> > dp_x1y3_romDO;
	sc_signal<bool> dp_x1y3_romEN;
	sc_signal<bool> dp_x1y3_romCLK;
	sc_signal<bool> dp_x1y3_romWE;
	sc_signal<bool> dp_x1y3_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y3_xDO;
	sc_signal< sc_uint<32> > dp_x1y3_xADDR;
	sc_signal< bool > dp_x1y3_xCLK, dp_x1y3_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y4_ramADDR;
	sc_signal<sc_int<32> > dp_x1y4_ramDI;
	sc_signal<sc_int<32> > dp_x1y4_ramDO;
	sc_signal<bool> dp_x1y4_ramEN;
	sc_signal<bool> dp_x1y4_ramCLK;
	sc_signal<bool> dp_x1y4_ramWE;
	sc_signal<bool> dp_x1y4_ramRST;
	sc_signal<sc_uint<32> > dp_x1y4_romADDR;
	sc_signal<sc_int<32> > dp_x1y4_romDI;
	sc_signal<sc_int<32> > dp_x1y4_romDO;
	sc_signal<bool> dp_x1y4_romEN;
	sc_signal<bool> dp_x1y4_romCLK;
	sc_signal<bool> dp_x1y4_romWE;