_network2x2.cpp

国外开源的一个片上网络系统的源代码

	NETWORK2x2 network2x2("network2x2");

	NETmMIPS dp_x0y0("dp_x0y0");
	NETmMIPS dp_x0y1("dp_x0y1");
	NETmMIPS dp_x1y0("dp_x1y0");
	NETmMIPS dp_x1y1("dp_x1y1");
	sc_signal< sc_bv<FLIT_LEN> > x0y0din;
	sc_signal< sc_bv<FLIT_LEN> > x0y0dout;
	sc_signal< bool > x0y0req_net;
	sc_signal< bool > x0y0ack_net;
	sc_signal< bool > x0y0ack_dp;
	sc_signal< bool > x0y0req_dp;

	sc_signal< sc_bv<FLIT_LEN> > x0y1din;
	sc_signal< sc_bv<FLIT_LEN> > x0y1dout;
	sc_signal< bool > x0y1req_net;
	sc_signal< bool > x0y1ack_net;
	sc_signal< bool > x0y1ack_dp;
	sc_signal< bool > x0y1req_dp;

	sc_signal< sc_bv<FLIT_LEN> > x1y0din;
	sc_signal< sc_bv<FLIT_LEN> > x1y0dout;
	sc_signal< bool > x1y0req_net;
	sc_signal< bool > x1y0ack_net;
	sc_signal< bool > x1y0ack_dp;
	sc_signal< bool > x1y0req_dp;

	sc_signal< sc_bv<FLIT_LEN> > x1y1din;
	sc_signal< sc_bv<FLIT_LEN> > x1y1dout;
	sc_signal< bool > x1y1req_net;
	sc_signal< bool > x1y1ack_net;
	sc_signal< bool > x1y1ack_dp;
	sc_signal< bool > x1y1req_dp;

	network2x2.clk(clk); network2x2.rst(rst);
	network2x2.x0y0din(x0y0din);
	network2x2.x0y0dout(x0y0dout);
	network2x2.x0y0req_net(x0y0req_net);
	network2x2.x0y0ack_net(x0y0ack_net);
	network2x2.x0y0ack_dp(x0y0ack_dp);
	network2x2.x0y0req_dp(x0y0req_dp);
	network2x2.x0y1din(x0y1din);
	network2x2.x0y1dout(x0y1dout);
	network2x2.x0y1req_net(x0y1req_net);
	network2x2.x0y1ack_net(x0y1ack_net);
	network2x2.x0y1ack_dp(x0y1ack_dp);
	network2x2.x0y1req_dp(x0y1req_dp);
	network2x2.x1y0din(x1y0din);
	network2x2.x1y0dout(x1y0dout);
	network2x2.x1y0req_net(x1y0req_net);
	network2x2.x1y0ack_net(x1y0ack_net);
	network2x2.x1y0ack_dp(x1y0ack_dp);
	network2x2.x1y0req_dp(x1y0req_dp);
	network2x2.x1y1din(x1y1din);
	network2x2.x1y1dout(x1y1dout);
	network2x2.x1y1req_net(x1y1req_net);
	network2x2.x1y1ack_net(x1y1ack_net);
	network2x2.x1y1ack_dp(x1y1ack_dp);
	network2x2.x1y1req_dp(x1y1req_dp);
	dp_x0y0.clock(clk); dp_x0y0.reset(rst); dp_x0y0.enable(en);
	dp_x0y1.clock(clk); dp_x0y1.reset(rst); dp_x0y1.enable(en);
	dp_x1y0.clock(clk); dp_x1y0.reset(rst); dp_x1y0.enable(en);
	dp_x1y1.clock(clk); dp_x1y1.reset(rst); dp_x1y1.enable(en);
	dp_x0y0.data_in(x0y0dout);
	dp_x0y0.data_out(x0y0din);
	dp_x0y0.req_out(x0y0req_net);
	dp_x0y0.ack_in(x0y0ack_net);
	dp_x0y0.ack_out(x0y0ack_dp);
	dp_x0y0.req_in(x0y0req_dp);

	dp_x0y1.data_in(x0y1dout);
	dp_x0y1.data_out(x0y1din);
	dp_x0y1.req_out(x0y1req_net);
	dp_x0y1.ack_in(x0y1ack_net);
	dp_x0y1.ack_out(x0y1ack_dp);
	dp_x0y1.req_in(x0y1req_dp);

	dp_x1y0.data_in(x1y0dout);
	dp_x1y0.data_out(x1y0din);
	dp_x1y0.req_out(x1y0req_net);
	dp_x1y0.ack_in(x1y0ack_net);
	dp_x1y0.ack_out(x1y0ack_dp);
	dp_x1y0.req_in(x1y0req_dp);

	dp_x1y1.data_in(x1y1dout);
	dp_x1y1.data_out(x1y1din);
	dp_x1y1.req_out(x1y1req_net);
	dp_x1y1.ack_in(x1y1ack_net);
	dp_x1y1.ack_out(x1y1ack_dp);
	dp_x1y1.req_in(x1y1req_dp);

	sc_signal<sc_uint<32> > dp_x0y0_ramADDR;
	sc_signal<sc_int<32> > dp_x0y0_ramDI;
	sc_signal<sc_int<32> > dp_x0y0_ramDO;
	sc_signal<bool> dp_x0y0_ramEN;
	sc_signal<bool> dp_x0y0_ramCLK;
	sc_signal<bool> dp_x0y0_ramWE;
	sc_signal<bool> dp_x0y0_ramRST;
	sc_signal<sc_uint<32> > dp_x0y0_romADDR;
	sc_signal<sc_int<32> > dp_x0y0_romDI;
	sc_signal<sc_int<32> > dp_x0y0_romDO;
	sc_signal<bool> dp_x0y0_romEN;
	sc_signal<bool> dp_x0y0_romCLK;
	sc_signal<bool> dp_x0y0_romWE;
	sc_signal<bool> dp_x0y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y0_xDO;
	sc_signal< sc_uint<32> > dp_x0y0_xADDR;
	sc_signal< bool > dp_x0y0_xCLK, dp_x0y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x0y1_ramADDR;
	sc_signal<sc_int<32> > dp_x0y1_ramDI;
	sc_signal<sc_int<32> > dp_x0y1_ramDO;
	sc_signal<bool> dp_x0y1_ramEN;
	sc_signal<bool> dp_x0y1_ramCLK;
	sc_signal<bool> dp_x0y1_ramWE;
	sc_signal<bool> dp_x0y1_ramRST;
	sc_signal<sc_uint<32> > dp_x0y1_romADDR;
	sc_signal<sc_int<32> > dp_x0y1_romDI;
	sc_signal<sc_int<32> > dp_x0y1_romDO;
	sc_signal<bool> dp_x0y1_romEN;
	sc_signal<bool> dp_x0y1_romCLK;
	sc_signal<bool> dp_x0y1_romWE;
	sc_signal<bool> dp_x0y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x0y1_xDO;
	sc_signal< sc_uint<32> > dp_x0y1_xADDR;
	sc_signal< bool > dp_x0y1_xCLK, dp_x0y1_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y0_ramADDR;
	sc_signal<sc_int<32> > dp_x1y0_ramDI;
	sc_signal<sc_int<32> > dp_x1y0_ramDO;
	sc_signal<bool> dp_x1y0_ramEN;
	sc_signal<bool> dp_x1y0_ramCLK;
	sc_signal<bool> dp_x1y0_ramWE;
	sc_signal<bool> dp_x1y0_ramRST;
	sc_signal<sc_uint<32> > dp_x1y0_romADDR;
	sc_signal<sc_int<32> > dp_x1y0_romDI;
	sc_signal<sc_int<32> > dp_x1y0_romDO;
	sc_signal<bool> dp_x1y0_romEN;
	sc_signal<bool> dp_x1y0_romCLK;
	sc_signal<bool> dp_x1y0_romWE;
	sc_signal<bool> dp_x1y0_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y0_xDO;
	sc_signal< sc_uint<32> > dp_x1y0_xADDR;
	sc_signal< bool > dp_x1y0_xCLK, dp_x1y0_xWE;
#endif

	sc_signal<sc_uint<32> > dp_x1y1_ramADDR;
	sc_signal<sc_int<32> > dp_x1y1_ramDI;
	sc_signal<sc_int<32> > dp_x1y1_ramDO;
	sc_signal<bool> dp_x1y1_ramEN;
	sc_signal<bool> dp_x1y1_ramCLK;
	sc_signal<bool> dp_x1y1_ramWE;
	sc_signal<bool> dp_x1y1_ramRST;
	sc_signal<sc_uint<32> > dp_x1y1_romADDR;
	sc_signal<sc_int<32> > dp_x1y1_romDI;
	sc_signal<sc_int<32> > dp_x1y1_romDO;
	sc_signal<bool> dp_x1y1_romEN;
	sc_signal<bool> dp_x1y1_romCLK;
	sc_signal<bool> dp_x1y1_romWE;
	sc_signal<bool> dp_x1y1_romRST;
#ifdef USEXRAM
	sc_signal< sc_int<32> > dp_x1y1_xDO;
	sc_signal< sc_uint<32> > dp_x1y1_xADDR;
	sc_signal< bool > dp_x1y1_xCLK, dp_x1y1_xWE;
#endif

	dp_x0y0.ramADDR(dp_x0y0_ramADDR);
	dp_x0y0.ramDI(dp_x0y0_ramDI);
	dp_x0y0.ramDO(dp_x0y0_ramDO);
	dp_x0y0.ramEN(dp_x0y0_ramEN);
	dp_x0y0.ramCLK(dp_x0y0_ramCLK);
	dp_x0y0.ramWE(dp_x0y0_ramWE);
	dp_x0y0.ramRST(dp_x0y0_ramRST);
	dp_x0y0.romADDR(dp_x0y0_romADDR);
	dp_x0y0.romDI(dp_x0y0_romDI);
	dp_x0y0.romDO(dp_x0y0_romDO);
	dp_x0y0.romEN(dp_x0y0_romEN);
	dp_x0y0.romCLK(dp_x0y0_romCLK);
	dp_x0y0.romWE(dp_x0y0_romWE);
	dp_x0y0.romRST(dp_x0y0_romRST);
#ifdef USEXRAM
	dp_x0y0.xADDR(dp_x0y0_xADDR);
	dp_x0y0.xDO(dp_x0y0_xDO);
	dp_x0y0.xCLK(dp_x0y0_xCLK);
	dp_x0y0.xWE(dp_x0y0_xWE);
#endif

	dp_x0y1.ramADDR(dp_x0y1_ramADDR);
	dp_x0y1.ramDI(dp_x0y1_ramDI);
	dp_x0y1.ramDO(dp_x0y1_ramDO);
	dp_x0y1.ramEN(dp_x0y1_ramEN);
	dp_x0y1.ramCLK(dp_x0y1_ramCLK);
	dp_x0y1.ramWE(dp_x0y1_ramWE);
	dp_x0y1.ramRST(dp_x0y1_ramRST);
	dp_x0y1.romADDR(dp_x0y1_romADDR);
	dp_x0y1.romDI(dp_x0y1_romDI);
	dp_x0y1.romDO(dp_x0y1_romDO);
	dp_x0y1.romEN(dp_x0y1_romEN);
	dp_x0y1.romCLK(dp_x0y1_romCLK);
	dp_x0y1.romWE(dp_x0y1_romWE);
	dp_x0y1.romRST(dp_x0y1_romRST);
#ifdef USEXRAM
	dp_x0y1.xADDR(dp_x0y1_xADDR);
	dp_x0y1.xDO(dp_x0y1_xDO);
	dp_x0y1.xCLK(dp_x0y1_xCLK);
	dp_x0y1.xWE(dp_x0y1_xWE);
#endif

	dp_x1y0.ramADDR(dp_x1y0_ramADDR);
	dp_x1y0.ramDI(dp_x1y0_ramDI);
	dp_x1y0.ramDO(dp_x1y0_ramDO);
	dp_x1y0.ramEN(dp_x1y0_ramEN);
	dp_x1y0.ramCLK(dp_x1y0_ramCLK);
	dp_x1y0.ramWE(dp_x1y0_ramWE);
	dp_x1y0.ramRST(dp_x1y0_ramRST);
	dp_x1y0.romADDR(dp_x1y0_romADDR);
	dp_x1y0.romDI(dp_x1y0_romDI);
	dp_x1y0.romDO(dp_x1y0_romDO);
	dp_x1y0.romEN(dp_x1y0_romEN);
	dp_x1y0.romCLK(dp_x1y0_romCLK);
	dp_x1y0.romWE(dp_x1y0_romWE);
	dp_x1y0.romRST(dp_x1y0_romRST);
#ifdef USEXRAM
	dp_x1y0.xADDR(dp_x1y0_xADDR);
	dp_x1y0.xDO(dp_x1y0_xDO);
	dp_x1y0.xCLK(dp_x1y0_xCLK);
	dp_x1y0.xWE(dp_x1y0_xWE);
#endif

	dp_x1y1.ramADDR(dp_x1y1_ramADDR);
	dp_x1y1.ramDI(dp_x1y1_ramDI);
	dp_x1y1.ramDO(dp_x1y1_ramDO);
	dp_x1y1.ramEN(dp_x1y1_ramEN);
	dp_x1y1.ramCLK(dp_x1y1_ramCLK);
	dp_x1y1.ramWE(dp_x1y1_ramWE);
	dp_x1y1.ramRST(dp_x1y1_ramRST);
	dp_x1y1.romADDR(dp_x1y1_romADDR);
	dp_x1y1.romDI(dp_x1y1_romDI);
	dp_x1y1.romDO(dp_x1y1_romDO);
	dp_x1y1.romEN(dp_x1y1_romEN);
	dp_x1y1.romCLK(dp_x1y1_romCLK);
	dp_x1y1.romWE(dp_x1y1_romWE);
	dp_x1y1.romRST(dp_x1y1_romRST);
#ifdef USEXRAM
	dp_x1y1.xADDR(dp_x1y1_xADDR);
	dp_x1y1.xDO(dp_x1y1_xDO);
	dp_x1y1.xCLK(dp_x1y1_xCLK);
	dp_x1y1.xWE(dp_x1y1_xWE);
#endif

	sc_signal< sc_bv<32> > dp_x0y0_pc;
	dp_x0y0.bus_pc(dp_x0y0_pc);
	sc_signal< sc_bv<32> > dp_x0y1_pc;
	dp_x0y1.bus_pc(dp_x0y1_pc);
	sc_signal< sc_bv<32> > dp_x1y0_pc;
	dp_x1y0.bus_pc(dp_x1y0_pc);
	sc_signal< sc_bv<32> > dp_x1y1_pc;
	dp_x1y1.bus_pc(dp_x1y1_pc);
#ifndef NOVCD
	sc_trace(tf, x0y0din, "dp_x0y0.net.x0y0din");
	sc_trace(tf, x0y0dout, "dp_x0y0.net.x0y0dout");
	sc_trace(tf, x0y0req_net, "dp_x0y0.net.x0y0req_net");
	sc_trace(tf, x0y0ack_net, "dp_x0y0.net.x0y0ack_net");
	sc_trace(tf, x0y0req_dp, "dp_x0y0.net.x0y0req_dp");
	sc_trace(tf, x0y0ack_dp, "dp_x0y0.net.x0y0ack_dp");

	sc_trace(tf, x0y1din, "dp_x0y1.net.x0y1din");
	sc_trace(tf, x0y1dout, "dp_x0y1.net.x0y1dout");
	sc_trace(tf, x0y1req_net, "dp_x0y1.net.x0y1req_net");
	sc_trace(tf, x0y1ack_net, "dp_x0y1.net.x0y1ack_net");
	sc_trace(tf, x0y1req_dp, "dp_x0y1.net.x0y1req_dp");
	sc_trace(tf, x0y1ack_dp, "dp_x0y1.net.x0y1ack_dp");

	sc_trace(tf, x1y0din, "dp_x1y0.net.x1y0din");
	sc_trace(tf, x1y0dout, "dp_x1y0.net.x1y0dout");
	sc_trace(tf, x1y0req_net, "dp_x1y0.net.x1y0req_net");
	sc_trace(tf, x1y0ack_net, "dp_x1y0.net.x1y0ack_net");
	sc_trace(tf, x1y0req_dp, "dp_x1y0.net.x1y0req_dp");
	sc_trace(tf, x1y0ack_dp, "dp_x1y0.net.x1y0ack_dp");

	sc_trace(tf, x1y1din, "dp_x1y1.net.x1y1din");
	sc_trace(tf, x1y1dout, "dp_x1y1.net.x1y1dout");
	sc_trace(tf, x1y1req_net, "dp_x1y1.net.x1y1req_net");
	sc_trace(tf, x1y1ack_net, "dp_x1y1.net.x1y1ack_net");
	sc_trace(tf, x1y1req_dp, "dp_x1y1.net.x1y1req_dp");
	sc_trace(tf, x1y1ack_dp, "dp_x1y1.net.x1y1ack_dp");

	sc_trace(tf, network2x2.x0y0_x1y0_data, "network2x2.x0y0_x1y0.x0y0_x1y0_data");
	sc_trace(tf, network2x2.x0y0_x1y0_ch0req, "network2x2.x0y0_x1y0.x0y0_x1y0_ch0req");
	sc_trace(tf, network2x2.x0y0_x1y0_ch0ack, "network2x2.x0y0_x1y0.x0y0_x1y0_ch0ack");
	sc_trace(tf, network2x2.x0y0_x1y0_ch1req, "network2x2.x0y0_x1y0.x0y0_x1y0_ch1req");
	sc_trace(tf, network2x2.x0y0_x1y0_ch1ack, "network2x2.x0y0_x1y0.x0y0_x1y0_ch1ack");
	sc_trace(tf, network2x2.x0y0_x0y1_data, "network2x2.x0y0_x0y1.x0y0_x0y1_data");
	sc_trace(tf, network2x2.x0y0_x0y1_ch0req, "network2x2.x0y0_x0y1.x0y0_x0y1_ch0req");
	sc_trace(tf, network2x2.x0y0_x0y1_ch0ack, "network2x2.x0y0_x0y1.x0y0_x0y1_ch0ack");
	sc_trace(tf, network2x2.x0y0_x0y1_ch1req, "network2x2.x0y0_x0y1.x0y0_x0y1_ch1req");
	sc_trace(tf, network2x2.x0y0_x0y1_ch1ack, "network2x2.x0y0_x0y1.x0y0_x0y1_ch1ack");
	sc_trace(tf, network2x2.x0y1_x1y1_data, "network2x2.x0y1_x1y1.x0y1_x1y1_data");
	sc_trace(tf, network2x2.x0y1_x1y1_ch0req, "network2x2.x0y1_x1y1.x0y1_x1y1_ch0req");
	sc_trace(tf, network2x2.x0y1_x1y1_ch0ack, "network2x2.x0y1_x1y1.x0y1_x1y1_ch0ack");
	sc_trace(tf, network2x2.x0y1_x1y1_ch1req, "network2x2.x0y1_x1y1.x0y1_x1y1_ch1req");
	sc_trace(tf, network2x2.x0y1_x1y1_ch1ack, "network2x2.x0y1_x1y1.x0y1_x1y1_ch1ack");
	sc_trace(tf, network2x2.x0y1_x0y0_data, "network2x2.x0y1_x0y0.x0y1_x0y0_data");
	sc_trace(tf, network2x2.x0y1_x0y0_ch0req, "network2x2.x0y1_x0y0.x0y1_x0y0_ch0req");
	sc_trace(tf, network2x2.x0y1_x0y0_ch0ack, "network2x2.x0y1_x0y0.x0y1_x0y0_ch0ack");
	sc_trace(tf, network2x2.x0y1_x0y0_ch1req, "network2x2.x0y1_x0y0.x0y1_x0y0_ch1req");
	sc_trace(tf, network2x2.x0y1_x0y0_ch1ack, "network2x2.x0y1_x0y0.x0y1_x0y0_ch1ack");
	sc_trace(tf, network2x2.x1y0_x0y0_data, "network2x2.x1y0_x0y0.x1y0_x0y0_data");
	sc_trace(tf, network2x2.x1y0_x0y0_ch0req, "network2x2.x1y0_x0y0.x1y0_x0y0_ch0req");
	sc_trace(tf, network2x2.x1y0_x0y0_ch0ack, "network2x2.x1y0_x0y0.x1y0_x0y0_ch0ack");
	sc_trace(tf, network2x2.x1y0_x0y0_ch1req, "network2x2.x1y0_x0y0.x1y0_x0y0_ch1req");
	sc_trace(tf, network2x2.x1y0_x0y0_ch1ack, "network2x2.x1y0_x0y0.x1y0_x0y0_ch1ack");
	sc_trace(tf, network2x2.x1y0_x1y1_data, "network2x2.x1y0_x1y1.x1y0_x1y1_data");
	sc_trace(tf, network2x2.x1y0_x1y1_ch0req, "network2x2.x1y0_x1y1.x1y0_x1y1_ch0req");
	sc_trace(tf, network2x2.x1y0_x1y1_ch0ack, "network2x2.x1y0_x1y1.x1y0_x1y1_ch0ack");
	sc_trace(tf, network2x2.x1y0_x1y1_ch1req, "network2x2.x1y0_x1y1.x1y0_x1y1_ch1req");
	sc_trace(tf, network2x2.x1y0_x1y1_ch1ack, "network2x2.x1y0_x1y1.x1y0_x1y1_ch1ack");
	sc_trace(tf, network2x2.x1y1_x0y1_data, "network2x2.x1y1_x0y1.x1y1_x0y1_data");
	sc_trace(tf, network2x2.x1y1_x0y1_ch0req, "network2x2.x1y1_x0y1.x1y1_x0y1_ch0req");
	sc_trace(tf, network2x2.x1y1_x0y1_ch0ack, "network2x2.x1y1_x0y1.x1y1_x0y1_ch0ack");
	sc_trace(tf, network2x2.x1y1_x0y1_ch1req, "network2x2.x1y1_x0y1.x1y1_x0y1_ch1req");
	sc_trace(tf, network2x2.x1y1_x0y1_ch1ack, "network2x2.x1y1_x0y1.x1y1_x0y1_ch1ack");
	sc_trace(tf, network2x2.x1y1_x1y0_data, "network2x2.x1y1_x1y0.x1y1_x1y0_data");
	sc_trace(tf, network2x2.x1y1_x1y0_ch0req, "network2x2.x1y1_x1y0.x1y1_x1y0_ch0req");
	sc_trace(tf, network2x2.x1y1_x1y0_ch0ack, "network2x2.x1y1_x1y0.x1y1_x1y0_ch0ack");
	sc_trace(tf, network2x2.x1y1_x1y0_ch1req, "network2x2.x1y1_x1y0.x1y1_x1y0_ch1req");
	sc_trace(tf, network2x2.x1y1_x1y0_ch1ack, "network2x2.x1y1_x1y0.x1y1_x1y0_ch1ack");

	trace_router(tf, network2x2.x0y0, "network2x2.x0y0.");
	trace_router(tf, network2x2.x0y1, "network2x2.x0y1.");
	trace_router(tf, network2x2.x1y0, "network2x2.x1y0.");
	trace_router(tf, network2x2.x1y1, "network2x2.x1y1.");
	trace_netmips(tf, &dp_x0y0, "dp_x0y0.mips_if.");
	trace_netif(tf, dp_x0y0.netif, "dp_x0y0.netif.");
#ifdef CACHE
	trace_mips(tf, dp_x0y0.mips->mips, "dp_x0y0.mips.");
#else
	trace_mips(tf, dp_x0y0.mips, "dp_x0y0.mips.");
//tracing one processor's memdev is sufficient to show the behavior of memdev module
	trace_memdev(tf, dp_x0y0.mips->memdev, "dp_x0y0.mips.memdev.");
#endif
	trace_netmips(tf, &dp_x0y1, "dp_x0y1.mips_if.");
	trace_netif(tf, dp_x0y1.netif, "dp_x0y1.netif.");
#ifdef CACHE
	trace_mips(tf, dp_x0y1.mips->mips, "dp_x0y1.mips.");
#else
	trace_mips(tf, dp_x0y1.mips, "dp_x0y1.mips.");
#endif
	trace_netmips(tf, &dp_x1y0, "dp_x1y0.mips_if.");
	trace_netif(tf, dp_x1y0.netif, "dp_x1y0.netif.");
#ifdef CACHE
	trace_mips(tf, dp_x1y0.mips->mips, "dp_x1y0.mips.");
#else
	trace_mips(tf, dp_x1y0.mips, "dp_x1y0.mips.");
#endif
	trace_netmips(tf, &dp_x1y1, "dp_x1y1.mips_if.");
	trace_netif(tf, dp_x1y1.netif, "dp_x1y1.netif.");
#ifdef CACHE
	trace_mips(tf, dp_x1y1.mips->mips, "dp_x1y1.mips.");
#else
	trace_mips(tf, dp_x1y1.mips, "dp_x1y1.mips.");
#endif
#endif
#ifndef CACHE
	dp_x0y0.mips->imem->mem_init("mips_rom.x0y0.bin");
	dp_x0y0.mips->imem->mem_dump("mips_rom.x0y0.0.dump");
	dp_x0y0.mips->dmem->mem_init("mips_ram.x0y0.bin");
	dp_x0y0.mips->dmem->mem_dump("mips_ram.x0y0.0.dump");
	dp_x0y1.mips->imem->mem_init("mips_rom.x0y1.bin");
	dp_x0y1.mips->imem->mem_dump("mips_rom.x0y1.0.dump");
	dp_x0y1.mips->dmem->mem_init("mips_ram.x0y1.bin");
	dp_x0y1.mips->dmem->mem_dump("mips_ram.x0y1.0.dump");
	dp_x1y0.mips->imem->mem_init("mips_rom.x1y0.bin");
	dp_x1y0.mips->imem->mem_dump("mips_rom.x1y0.0.dump");
	dp_x1y0.mips->dmem->mem_init("mips_ram.x1y0.bin");
	dp_x1y0.mips->dmem->mem_dump("mips_ram.x1y0.0.dump");
	dp_x1y1.mips->imem->mem_init("mips_rom.x1y1.bin");
	dp_x1y1.mips->imem->mem_dump("mips_rom.x1y1.0.dump");
	dp_x1y1.mips->dmem->mem_init("mips_ram.x1y1.bin");
	dp_x1y1.mips->dmem->mem_dump("mips_ram.x1y1.0.dump");
#else
	dp_x0y0.mips->memory->memory->mem_init("mem.x0y0.bin");
	dp_x0y0.mips->memory->memory->mem_dump("mem.x0y0.0.dump");
	dp_x0y1.mips->memory->memory->mem_init("mem.x0y1.bin");
	dp_x0y1.mips->memory->memory->mem_dump("mem.x0y1.0.dump");
	dp_x1y0.mips->memory->memory->mem_init("mem.x1y0.bin");
	dp_x1y0.mips->memory->memory->mem_dump("mem.x1y0.0.dump");
	dp_x1y1.mips->memory->memory->mem_init("mem.x1y1.bin");
	dp_x1y1.mips->memory->memory->mem_dump("mem.x1y1.0.dump");
#endif