bram16k.h

国外开源的一个片上网络系统的源代码

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   
 *
 *  Author          :   [e-mail]
 *
 *  Date            :   
 *
 *  Function        :   RAM based on VirtexII 16kb BlockRAMs
 *                      Uses 32 blocks of 1-bit-wide memory
 *
 */
 
#ifndef BRAM16K_H_INCLUDED
#define BRAM16K_H_INCLUDED

#include "xlxram.h"

SC_MODULE(BRAM16K_WRAPPER) {
	sc_in <	sc_bv<32> > addr;
	sc_out< sc_bv<32> > dout;
	sc_in< sc_bv<32> > din;

	sc_in<	sc_bv<W_MEMWRITE>	 > w;
	sc_in<	sc_bv<W_MEMREAD>	 > r;
	sc_in<	bool		 > clk;

	sc_in< sc_bv<1> > en;
	sc_out< bool > memwait;

	sc_out<sc_uint<12> > ADDR;
	sc_out<sc_int<4> > DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07;
	sc_out<bool> EN, CLK, SSR, WE0, WE1, WE2, WE3;
	sc_in<sc_int<4> > DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07;

	sc_signal<sc_bv<2> > byte_reg;
	sc_signal<sc_bv<W_MEMWRITE> > w_reg;
	sc_signal<sc_bv<W_MEMREAD> > r_reg;
	
	void in();
	void out();
	void reg();
	
	SC_CTOR(BRAM16K_WRAPPER) {
	  
	  SC_METHOD(in);
	  sensitive << addr << din << w << r << en << clk;
	  
	  SC_METHOD(out);
	  sensitive << DO00 << DO01 << DO02 << DO03 << DO04 << DO05 << DO06 << DO07 
				<< w_reg << r_reg << byte_reg;
	  
	  SC_METHOD(reg);
	  sensitive_pos << clk;
	};
	
};

// Converter for the debugging access
SC_MODULE(BRAM16K_DBGWRAPPER) {

  sc_out<sc_int<32> > DO;
  sc_in<sc_uint<32> > ADDR;
  sc_in<sc_int<32> > DI;
  sc_in<bool> EN;
  sc_in<bool> CLK;
  sc_in<bool> WE;
  sc_in<bool> RST;

  sc_out<sc_uint<12> > dADDR;
  sc_out<sc_int<4> > dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07;
  sc_out<bool> dEN, dCLK, dSSR, dWE;
  sc_in<sc_int<4> > dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07;

  void in();
  void out();
	
  SC_CTOR(BRAM16K_DBGWRAPPER) {  
	SC_METHOD(in);
	sensitive << ADDR << DI << EN << WE << RST << CLK;
	  
	SC_METHOD(out);
	sensitive << dDO00 << dDO01 << dDO02 << dDO03 << dDO04 << dDO05 << dDO06 << dDO07;
  };
	
};

SC_MODULE(BRAM16K) {
	sc_in <	sc_bv<32> > addr;
	sc_out< sc_bv<32> > dout;
	sc_in< sc_bv<32> > din;

	sc_in<	sc_bv<W_MEMWRITE>	 > w;
	sc_in<	sc_bv<W_MEMREAD>	 > r;
	sc_in<	bool		 > clk;

	sc_in< sc_bv<1> > en;
	sc_out< bool > memwait;

	// memory bits - bram00 keeps bit at address 00, so its MSB (BIGENDIAN)
	RAMB16_S4_S4 *bram00, *bram01, *bram02, *bram03, *bram04, *bram05, *bram06, *bram07;
	BRAM16K_WRAPPER *conv;
	
	sc_signal<sc_uint<12> > ADDR;
	sc_signal<sc_int<4> > DI00, DI01, DI02, DI03, DI04, DI05, DI06, DI07;
	sc_signal<bool> EN, CLK, SSR, WE0, WE1, WE2, WE3;
	sc_signal<sc_int<4> > DO00, DO01, DO02, DO03, DO04, DO05, DO06, DO07;

	BRAM16K_DBGWRAPPER *dbgconv;
	
	// independent access to the second set of ports for debugging
	
	sc_out<sc_int<32> > dbgDO;
	sc_in<sc_uint<32> > dbgADDR;
	sc_in<sc_int<32> > dbgDI;
	sc_in<bool> dbgEN;
	sc_in<bool> dbgCLK;
	sc_in<bool> dbgWE;
	sc_in<bool> dbgRST;

	sc_signal<sc_uint<12> > dADDR;
	sc_signal<sc_int<4> > dDI00, dDI01, dDI02, dDI03, dDI04, dDI05, dDI06, dDI07;
	sc_signal<bool> dEN, dCLK, dSSR, dWE;
	sc_signal<sc_int<4> > dDO00, dDO01, dDO02, dDO03, dDO04, dDO05, dDO06, dDO07;
	
#ifndef VERILOG
	void mem_init(const char *filename, int size=16384);
	void mem_dump(const char *filename, int size=16384);
#endif

	SC_CTOR(BRAM16K) {

	  bram00 = new RAMB16_S4_S4("bram00");
	  bram01 = new RAMB16_S4_S4("bram01");
	  bram02 = new RAMB16_S4_S4("bram02");
	  bram03 = new RAMB16_S4_S4("bram03");
	  bram04 = new RAMB16_S4_S4("bram04");
	  bram05 = new RAMB16_S4_S4("bram05");
	  bram06 = new RAMB16_S4_S4("bram06");
	  bram07 = new RAMB16_S4_S4("bram07");

	  conv = new BRAM16K_WRAPPER("conv");
	  conv->addr(addr);
	  conv->din(din);
	  conv->dout(dout);
	  conv->r(r);
	  conv->w(w);
	  conv->memwait(memwait);
	  conv->en(en);
	  conv->clk(clk);

	  dbgconv = new BRAM16K_DBGWRAPPER("dbgconv");
	  dbgconv->DO(dbgDO);
	  dbgconv->ADDR(dbgADDR);
	  dbgconv->DI(dbgDI);
	  dbgconv->EN(dbgEN);
	  dbgconv->CLK(dbgCLK);
	  dbgconv->WE(dbgWE);
	  dbgconv->RST(dbgRST);

	  
	  bram00->ADDRA(ADDR); bram00->ENA(EN); bram00->WEA(WE0); bram00->CLKA(CLK); bram00->SSRA(SSR);
	  bram01->ADDRA(ADDR); bram01->ENA(EN); bram01->WEA(WE0); bram01->CLKA(CLK); bram01->SSRA(SSR);
	  bram02->ADDRA(ADDR); bram02->ENA(EN); bram02->WEA(WE1); bram02->CLKA(CLK); bram02->SSRA(SSR);
	  bram03->ADDRA(ADDR); bram03->ENA(EN); bram03->WEA(WE1); bram03->CLKA(CLK); bram03->SSRA(SSR);
	  bram04->ADDRA(ADDR); bram04->ENA(EN); bram04->WEA(WE2); bram04->CLKA(CLK); bram04->SSRA(SSR);
	  bram05->ADDRA(ADDR); bram05->ENA(EN); bram05->WEA(WE2); bram05->CLKA(CLK); bram05->SSRA(SSR);
	  bram06->ADDRA(ADDR); bram06->ENA(EN); bram06->WEA(WE3); bram06->CLKA(CLK); bram06->SSRA(SSR);
	  bram07->ADDRA(ADDR); bram07->ENA(EN); bram07->WEA(WE3); bram07->CLKA(CLK); bram07->SSRA(SSR);
	  

	  bram00->DIA(DI00); bram00->DOA(DO00);
	  bram01->DIA(DI01); bram01->DOA(DO01);
	  bram02->DIA(DI02); bram02->DOA(DO02);
	  bram03->DIA(DI03); bram03->DOA(DO03);
	  bram04->DIA(DI04); bram04->DOA(DO04);
	  bram05->DIA(DI05); bram05->DOA(DO05);
	  bram06->DIA(DI06); bram06->DOA(DO06);
	  bram07->DIA(DI07); bram07->DOA(DO07);

	  conv->ADDR(ADDR); conv->EN(EN); conv->CLK(CLK); conv->SSR(SSR);
	  conv->WE3(WE3);
	  conv->WE2(WE2);
	  conv->WE1(WE1);
	  conv->WE0(WE0);
	  conv->DI00(DI00); conv->DO00(DO00);
	  conv->DI01(DI01); conv->DO01(DO01);
	  conv->DI02(DI02); conv->DO02(DO02);
	  conv->DI03(DI03); conv->DO03(DO03);
	  conv->DI04(DI04); conv->DO04(DO04);
	  conv->DI05(DI05); conv->DO05(DO05);
	  conv->DI06(DI06); conv->DO06(DO06);
	  conv->DI07(DI07); conv->DO07(DO07);
	  

	  bram00->ADDRB(dADDR); bram00->ENB(dEN); bram00->WEB(dWE); bram00->CLKB(dCLK); bram00->SSRB(dSSR);
	  bram01->ADDRB(dADDR); bram01->ENB(dEN); bram01->WEB(dWE); bram01->CLKB(dCLK); bram01->SSRB(dSSR);
	  bram02->ADDRB(dADDR); bram02->ENB(dEN); bram02->WEB(dWE); bram02->CLKB(dCLK); bram02->SSRB(dSSR);
	  bram03->ADDRB(dADDR); bram03->ENB(dEN); bram03->WEB(dWE); bram03->CLKB(dCLK); bram03->SSRB(dSSR);
	  bram04->ADDRB(dADDR); bram04->ENB(dEN); bram04->WEB(dWE); bram04->CLKB(dCLK); bram04->SSRB(dSSR);
	  bram05->ADDRB(dADDR); bram05->ENB(dEN); bram05->WEB(dWE); bram05->CLKB(dCLK); bram05->SSRB(dSSR);
	  bram06->ADDRB(dADDR); bram06->ENB(dEN); bram06->WEB(dWE); bram06->CLKB(dCLK); bram06->SSRB(dSSR);
	  bram07->ADDRB(dADDR); bram07->ENB(dEN); bram07->WEB(dWE); bram07->CLKB(dCLK); bram07->SSRB(dSSR);

	  bram00->DIB(dDI00); bram00->DOB(dDO00);
	  bram01->DIB(dDI01); bram01->DOB(dDO01);
	  bram02->DIB(dDI02); bram02->DOB(dDO02);
	  bram03->DIB(dDI03); bram03->DOB(dDO03);
	  bram04->DIB(dDI04); bram04->DOB(dDO04);
	  bram05->DIB(dDI05); bram05->DOB(dDO05);
	  bram06->DIB(dDI06); bram06->DOB(dDO06);
	  bram07->DIB(dDI07); bram07->DOB(dDO07);

	  dbgconv->dADDR(dADDR); dbgconv->dEN(dEN); dbgconv->dWE(dWE); dbgconv->dCLK(dCLK); dbgconv->dSSR(dSSR);
	  dbgconv->dDI00(dDI00); dbgconv->dDO00(dDO00);
	  dbgconv->dDI01(dDI01); dbgconv->dDO01(dDO01);
	  dbgconv->dDI02(dDI02); dbgconv->dDO02(dDO02);
	  dbgconv->dDI03(dDI03); dbgconv->dDO03(dDO03);
	  dbgconv->dDI04(dDI04); dbgconv->dDO04(dDO04);
	  dbgconv->dDI05(dDI05); dbgconv->dDO05(dDO05);
	  dbgconv->dDI06(dDI06); dbgconv->dDO06(dDO06);
	  dbgconv->dDI07(dDI07); dbgconv->dDO07(dDO07);
 
	};
};


#endif