cache_mips.h

国外开源的一个片上网络系统的源代码

/*
 *  TU Eindhoven
 *  Eindhoven, The Netherlands
 *
 *  Name            :   
 *
 *  Author          :   Aleksander Slusarczyk
 *
 *  Date            :   
 *
 *  Function        :   mMIPS with caches and local I/D memory
 *
 */


#ifndef CACHE_MIPS_H_INCLUDED
#define CACHE_MIPS_H_INCLUDED

#include "mmips.h"
#include "cache_mainmem.h"

SC_MODULE(CACHE_MIPS)
{
  mMIPS *mips;
  CACHE_MAINMEM *memory;

  sc_in<bool> clock;
  sc_in<bool> enable;
  sc_in<bool> reset;

  sc_out< sc_bv<32> > bus_pc;
  
  // signals to the network interface
  sc_out< sc_bv<DWORD> > dev_dout;
  sc_in< sc_bv<DWORD> > dev_din;
  sc_out< bool > dev_r, dev_w;
  sc_in< bool > dev_rdyr, dev_rdyw;
  sc_out< bool > dev_wdata, dev_waddr;
  sc_out<bool> dev_send_eop;
  sc_in<bool> dev_rcv_eop;

  // download/upload of local memory
  sc_in<sc_uint<32> > ramADDR;
  sc_in<sc_int<32> > ramDI;
  sc_out<sc_int<32> > ramDO;
  sc_in<bool> ramEN, ramCLK, ramWE, ramRST;

  // these are not used - only for interface compatible with 'regular' mips
  sc_in<sc_uint<32> > romADDR;
  sc_in<sc_int<32> > romDI;
  sc_out<sc_int<32> > romDO;
  sc_in<bool> romEN, romCLK, romWE, romRST;

#ifdef USEXRAM
  sc_out< sc_int<32> > xDO;
  sc_in< sc_uint<32> > xADDR;
  sc_in< bool > xCLK, xWE;
#endif
  
  // connection caches <-> local memory
  sc_signal< sc_bv<32> > cache_dout;

  sc_signal< sc_bv<32> > icache_addr, icache_din;
  sc_signal< bool > icache_ww, icache_wb, icache_r;
  sc_signal< bool > icache_rdy;

  sc_signal< sc_bv<32> > dcache_addr, dcache_din;
  sc_signal< bool > dcache_ww, dcache_wb, dcache_r;
  sc_signal< bool > dcache_rdy;

  SC_CTOR(CACHE_MIPS)
	{
	  mips = new mMIPS("mips");
	  memory = new CACHE_MAINMEM("local_memory");

	  mips->clock(clock);
	  mips->enable(enable);
	  mips->reset(reset);

	  mips->bus_pc(bus_pc);
	  
	  mips->dcache_addr(dcache_addr); 
	  mips->dcache_din(dcache_din); 
	  mips->dcache_dout(cache_dout); 
	  mips->dcache_ww(dcache_ww); 
	  mips->dcache_wb(dcache_wb); 
	  mips->dcache_r(dcache_r); 
	  mips->dcache_rdy(dcache_rdy); 

	  mips->icache_addr(icache_addr); 
	  mips->icache_din(icache_din); 
	  mips->icache_dout(cache_dout); 
	  mips->icache_ww(icache_ww); 
	  mips->icache_wb(icache_wb); 
	  mips->icache_r(icache_r); 
	  mips->icache_rdy(icache_rdy); 

	  mips->dev_dout(dev_dout);
	  mips->dev_din(dev_din);
	  mips->dev_r(dev_r);
	  mips->dev_w(dev_w);
	  mips->dev_rdyr(dev_rdyr);
	  mips->dev_rdyw(dev_rdyw);
	  mips->dev_wdata(dev_wdata);
	  mips->dev_waddr(dev_waddr);
	  mips->dev_send_eop(dev_send_eop);
	  mips->dev_rcv_eop(dev_rcv_eop);

	  memory->clk(clock);
	  memory->dout(cache_dout);

	  memory->addr0(icache_addr);
	  memory->din0(icache_din);
	  memory->ww0(icache_ww);
	  memory->wb0(icache_wb);
	  memory->r0(icache_r);
	  memory->rdy0(icache_rdy);

	  memory->addr1(dcache_addr);
	  memory->din1(dcache_din);
	  memory->ww1(dcache_ww);
	  memory->wb1(dcache_wb);
	  memory->r1(dcache_r);
	  memory->rdy1(dcache_rdy);

	  memory->ramDO(ramDO);
	  memory->ramADDR(ramADDR);
	  memory->ramDI(ramDI);
	  memory->ramEN(ramEN);
	  memory->ramCLK(ramCLK);
	  memory->ramWE(ramWE);
	  memory->ramRST(ramRST);

#ifdef USEXRAM
	  mips->xDO( xDO );
	  mips->xADDR( xADDR );
	  mips->xCLK( xCLK );
	  mips->xWE( xWE );
#endif

	}
};

#endif