adsp21xx.dsp

来自「著名的Handle」· DSP 代码 · 共 102 行

{*******************************************************************************
 *  Demonstration file for the ADSP21xxSyn syntax highlighter                  *
 *  Wynand Breytenbach    1999/12/9     [e-mail]                         *
 *                                                                             *
 *  The ADSP21xxSyn is a syntax highlighter for the family of fixed point      *
 *  Digital Signal Processors from Analog Devices                              *
 *                                                                             *
 *  Note: This code does not represent a valid program                         *
 *        This is an example of a multi line comment                           *
 ******************************************************************************}

#include <def2181.v14>
!*******************************************************************************
.module/ram/abs=0  Demo;
.var/dm/seg=dmDPR  DPR[1024];
.var/dm/abs=0x2000 idmaCmdParam;
.var/dm/abs=0x200b idmaRxDelay;
.var/dm            TimeRemaining,TimerState,IdleDelay;

.init              TVGValue        : 0;
.init              TimerState      : tsIdle;

!*************************Interupt vector table*********************************
PowerUp:                jump Initialize;  nop; nop; nop;
IRQ2:                   jump NetWorkISR;  nop; nop; nop;

Initialize:
  DMOVLAY = 1;  ! enable external DPR
  ar = 0x1007;  ! set DPR delay => 1, IO => 7
  dm(DmWaitReg) = ar;
  m0 = 0;
  m4 = 1;
  ifc = ciALL;

  !Get Hardware in the desired state:
    set fl0;             ! select TVG DAC
    icntl = 0;           ! no nesting of interrupts

    ! set up timer for 1 ms intervals
    SetupTimer:
    ar = 0;dm(TScaleReg) = ar;
    ar = 32000;dm(TPeriodReg) = ar;  ! first time
    dm(TCountReg) = ar;              ! following times

    ! Clear DPR
    cntr = 0x3fd; ! up to interrupt registers
    SrcPtr = ^DPR;
    do ClrDPR until ce;
    ClrDPR: dm(SrcPtr,m4) = ar;

    ena timer;
    !start the LAN Interface
    dm(IntrLAN) = ax0;

!*******************************************************************************
NetWorkISR:
! Occurs when the network is ready
  ena sec_reg;

    cntr = %SonCtrl;
    SrcPtr = DataX+TableOffset;
    DstPtr = ^LocalData;
    do ReadDPR until ce;
      sr1 = dm(SrcPtr,m4);
    ReadDPR: dm(DstPtr,m4) = sr1;
rti;

!*******************************************************************************
TimerISR:
  ena sec_reg;
  ! update buffer pointer
  modify(ADCPtr,m1);

  #ifdef PCGAINCONTROL
    ar  = dm(idmaGAIN);
    tx1 = ar;
  #else  !simulate
    ar  = dm(TVGValue);
    tx1 = ar;
    ar  = ar + 256;
    dm(TVGValue) = ar;
  #endif

  rti;

!*******************************************************************************
  ReadADCISR:
    ena sec_reg;
    ar = rx1;
    sr = lshift ar by 4(lo); ! make it a 16 bit number
    dm(ADCPtr,m0) = sr0;
    rti;

!*******************************************************************************
WaitTxDone:
  cntr = 0x50;
  do WaitTx1 until ce;
  WaitTx1: nop;
rts;

.endmod;