initspr.s

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;#************************************************************************
;#
;#	$Copyright    2001 Joseph J. Lemieux  ALL RIGHTS RESERVED. $
;#
;#	$Filename: C:\OSEKBook\src\CH09\src\initspr.s $
;#
;#   PURPOSE: Initialization of Special Purpose Registers. Must be 
;#            initialized manually.
;#                                                    
;#************************************************************************


   .text
   .globl   InitSPR
   .section ".text"
;/************************************************
;*
;*   Function:     InitSPR
;*
;*   Inputs:       none
;*
;*   Outputs:      SPRs are set as required
;*
;*   Returns:      none
;*
;*   Description:  Sets the Special Purpose Registers
;*
;************************************************/
InitSPR:
;#------------------------------------------------------------------------
;# Set the MSR and SRR1
;#------------------------------------------------------------------------
   	li      	r3,0x2100          ;# MSR,SRR1 = 0x0000 2100
   	mtmsr   	r3
   	mtspr   	SRR1,r3

;#------------------------------------------------------------------------
;# Initialize Core registers
;#------------------------------------------------------------------------
;# Set the decrementer (to a very high value to avoid interrupts during
;# these initializations)
;#------------------------------------------------------------------------
   	lis      	r3,%hiadj(0x7FFFFFFF)
	addi		r3,r3,0xFFFF
   	mtdec   	r3

;#------------------------------------------------------------------------
;# Set the Instruction Support Control Register (ICTRL):
;#   - Set Serialized Mode and No Show Cycle to work around some
;#      CPU hardware bugs. 
;#------------------------------------------------------------------------
   	li      	r3,0x0003          ;# ICTRL = 0x0000 0003
   	mtspr   	ICTRL,r3

;#------------------------------------------------------------------------
;# Set the Debug Enable Register (DER):
;#    - All debug interrupts are disabled; All events result in regular
;#   event handling 
;#------------------------------------------------------------------------
   	addi    	r3,r0,0            ;# DER = 0
   	mtspr   	DER,r3

	blr
	.end