spi.c

基于642的sd卡读写程序

#include <csl_mcbsp.h>   /* MCBSP_SUPPORT */
#include <csl_mcbsphal.h>
#include <csl.h>         /* CSL library   */
#include <csl_chip.h>
#include <csl_dat.h>
#include "sdconfig.h"
#include "sdhal.h"   
#include "sdcrc.h"   
#include "sdcmd.h"   

MCBSP_Handle hMcbsp0;       /* Handles for McBSP */
MCBSP_Handle init_mcbsp0_master(Uint8 y);
void init_mcbsp0_gpio(void);
MCBSP_Handle init_mcbsp01_master(void);



extern Uint8 clk;
MCBSP_Handle SPI_INIT(Uint8 x)
{
    //CSL_init();
    init_mcbsp0_master(x);
    EVMDM642_waitusec(100);
    MCBSP_enableSrgr(hMcbsp0);
    MCBSP_enableRcv(hMcbsp0); /* Enable McBSP channel                     */
    MCBSP_enableXmt(hMcbsp0); /* McBSP port 0 as the transmitter/receiver */
    EVMDM642_waitusec(100);
}

    
    MCBSP_Handle init_mcbsp0_master(Uint8 y)
{  
   if(y>0x50)
hMcbsp0 = MCBSP_open(1, MCBSP_OPEN_RESET); /* McBSP port 0             */


	if(hMcbsp0 == INV)
	{
		return (MCBSP_Handle)0xffff;
	}
	

MCBSP_configArgs(
                   hMcbsp0,
                   MCBSP_SPCR_RMK(
           MCBSP_SPCR_FREE_DEFAULT,
           MCBSP_SPCR_SOFT_DEFAULT,
           MCBSP_SPCR_FRST_DEFAULT,
           MCBSP_SPCR_GRST_DEFAULT,//should be 1 or 0?
           MCBSP_SPCR_XINTM_DEFAULT,
           MCBSP_SPCR_XSYNCERR_DEFAULT,
           MCBSP_SPCR_XRST_DEFAULT,
           MCBSP_SPCR_DLB_DEFAULT,
           0x02,//MCBSP_SPCR_RJUST_DEFAULT,
           0x2,//MCBSP_SPCR_CLKSTP_DELAY, /* CLKSTP=11b with CLKXP=0, clock starts with */
           MCBSP_SPCR_DXENA_OFF,    /* rising edge with delay                     */
           MCBSP_SPCR_RINTM_DEFAULT,
           MCBSP_SPCR_RSYNCERR_DEFAULT,
           MCBSP_SPCR_RRST_DEFAULT//need no modification
           ),
                  
    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_SINGLE,
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_NO,
           MCBSP_RCR_RDATDLY_1BIT,//原来是defaulet，自己改为1
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_8BIT,  /* receive element length phase 1 is 32 bits */
           MCBSP_RCR_RWDREVRS_DISABLE
           ),



    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_SINGLE,//default or single?
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1 bit data delay                    */
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_8BIT,   /* transmit element phase 1 is 32 bits or 8 bits? */
           MCBSP_XCR_XWDREVRS_DISABLE
           ),


     MCBSP_SRGR_RMK(
           MCBSP_SRGR_GSYNC_FREE,
           MCBSP_SRGR_CLKSP_RISING,
           0x01,//MCBSP_SRGR_CLKSM_EXTERNAL, /* SRGR clock mode from internal source */
           MCBSP_SRGR_FSGM_DEFAULT,//should be 0
           MCBSP_SRGR_FPER_DEFAULT,
           MCBSP_SRGR_FWID_DEFAULT,
           MCBSP_SRGR_CLKGDV_OF(y) /* 分频数值再议 */
           ),


     MCBSP_MCR_RMK(                  /* only for 64x                               */
           MCBSP_MCR_XMCME_DEFAULT,  /* All fields in MCR set to default values    */
           MCBSP_MCR_XPBBLK_DEFAULT,
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RMCME_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),



                
           MCBSP_RCERE0_RMK(0),      /* Additional registers only for 64x        */
           MCBSP_RCERE1_RMK(0),
           MCBSP_RCERE2_RMK(0),
           MCBSP_RCERE3_RMK(0),

           
        
           MCBSP_XCERE0_RMK(0),       /* Additional registers only for 64x       */
           MCBSP_XCERE1_RMK(0),
           MCBSP_XCERE2_RMK(0),
           MCBSP_XCERE3_RMK(0),
		   
		   
     MCBSP_PCR_RMK(
           MCBSP_PCR_XIOEN_SP,
           MCBSP_PCR_RIOEN_SP,
           MCBSP_PCR_FSXM_INTERNAL, /* frame sync generation               */
           MCBSP_PCR_FSRM_EXTERNAL, 
           MCBSP_PCR_CLKXM_OUTPUT,  /* tans. clock mode from internal SRGR */
           MCBSP_PCR_CLKRM_INPUT,
           MCBSP_PCR_CLKSSTAT_0,
           MCBSP_PCR_DXSTAT_0,
           MCBSP_PCR_FSXP_ACTIVELOW, /* active low trans. frame sync. polarity  */
           MCBSP_PCR_FSRP_ACTIVEHIGH,
           0x01,//MCBSP_PCR_CLKXP_RISING,  /* trans. clk pol. from rising edge of CLKX */
           MCBSP_PCR_CLKRP_FALLING
           )
            
           );
                   
//MCBSP_config(hMcbsp0,&mcbspCfg0);
}


void SPI_INIGP(void)
{
    //CSL_init();
    init_mcbsp0_gpio();
   // MCBSP_enableSrgr(hMcbsp0);
   // MCBSP_enableRcv(hMcbsp0); /* Enable McBSP channel                     */
   // MCBSP_enableXmt(hMcbsp0); /* McBSP port 0 as the transmitter/receiver */
    
}

    
    void init_mcbsp0_gpio(void)
{  
    MCBSP_Config mcbspCfg0 = {  /* SPI mode, CLKSTP = 11b and CLKXP = 0: Clock  */

    MCBSP_SPCR_RMK(
           MCBSP_SPCR_FREE_DEFAULT,
           MCBSP_SPCR_SOFT_DEFAULT,
           MCBSP_SPCR_FRST_DEFAULT,
           MCBSP_SPCR_GRST_DEFAULT,//should be 1 or 0?
           MCBSP_SPCR_XINTM_DEFAULT,
           MCBSP_SPCR_XSYNCERR_DEFAULT,
           MCBSP_SPCR_XRST_DEFAULT,
           MCBSP_SPCR_DLB_DEFAULT,
           MCBSP_SPCR_RJUST_DEFAULT,
           MCBSP_SPCR_CLKSTP_DELAY, /* CLKSTP=11b with CLKXP=0, clock starts with */
           MCBSP_SPCR_DXENA_OFF,    /* rising edge with delay                     */
           MCBSP_SPCR_RINTM_DEFAULT,
           MCBSP_SPCR_RSYNCERR_DEFAULT,
           MCBSP_SPCR_RRST_DEFAULT//need no modification
           ),



    MCBSP_RCR_RMK(
           MCBSP_RCR_RPHASE_SINGLE,
           MCBSP_RCR_RFRLEN2_DEFAULT,
           MCBSP_RCR_RWDLEN2_DEFAULT,
           MCBSP_RCR_RCOMPAND_DEFAULT,
           MCBSP_RCR_RFIG_NO,
           MCBSP_RCR_RDATDLY_1BIT,//原来是defaulet，自己改为1
           MCBSP_RCR_RFRLEN1_DEFAULT,
           MCBSP_RCR_RWDLEN1_8BIT,  /* receive element length phase 1 is 32 bits */
           MCBSP_RCR_RWDREVRS_DISABLE
           ),



    MCBSP_XCR_RMK(
           MCBSP_XCR_XPHASE_SINGLE,//default or single?
           MCBSP_XCR_XFRLEN2_DEFAULT,
           MCBSP_XCR_XWDLEN2_DEFAULT,
           MCBSP_XCR_XCOMPAND_DEFAULT,
           MCBSP_XCR_XFIG_DEFAULT,
           MCBSP_XCR_XDATDLY_1BIT,    /* 1 bit data delay                    */
           MCBSP_XCR_XFRLEN1_DEFAULT,
           MCBSP_XCR_XWDLEN1_8BIT,   /* transmit element phase 1 is 32 bits or 8 bits? */
           MCBSP_XCR_XWDREVRS_DISABLE
           ),


     MCBSP_SRGR_RMK(
           MCBSP_SRGR_GSYNC_FREE,
           MCBSP_SRGR_CLKSP_RISING,
           0x01,//MCBSP_SRGR_CLKSM_EXTERNAL, /* SRGR clock mode from internal source */
           MCBSP_SRGR_FSGM_DEFAULT,//should be 0
           MCBSP_SRGR_FPER_DEFAULT,
           MCBSP_SRGR_FWID_DEFAULT,
           MCBSP_SRGR_CLKGDV_OF(0x63) /* 分频数值再议 */
           ),


     MCBSP_MCR_RMK(                  /* only for 64x                               */
           MCBSP_MCR_XMCME_DEFAULT,  /* All fields in MCR set to default values    */
           MCBSP_MCR_XPBBLK_DEFAULT,
           MCBSP_MCR_XPABLK_DEFAULT,
           MCBSP_MCR_XMCM_DEFAULT,
           MCBSP_MCR_RPBBLK_DEFAULT,
           MCBSP_MCR_RMCME_DEFAULT,
           MCBSP_MCR_RPABLK_DEFAULT,
           MCBSP_MCR_RMCM_DEFAULT
           ),



                
           MCBSP_RCERE0_RMK(0),      /* Additional registers only for 64x        */
           MCBSP_RCERE1_RMK(0),
           MCBSP_RCERE2_RMK(0),
           MCBSP_RCERE3_RMK(0),

           
        
           MCBSP_XCERE0_RMK(0),       /* Additional registers only for 64x       */
           MCBSP_XCERE1_RMK(0),
           MCBSP_XCERE2_RMK(0),
           MCBSP_XCERE3_RMK(0),
		   
		   
     MCBSP_PCR_RMK(
           MCBSP_PCR_XIOEN_GPIO,
           MCBSP_PCR_RIOEN_GPIO,
           0x1,//MCBSP_PCR_FSXM_INTERNAL, /* frame sync generation               */
           0x1,//MCBSP_PCR_FSRM_EXTERNAL, 
           0x1,//MCBSP_PCR_CLKXM_OUTPUT,  /* tans. clock mode from internal SRGR */
           0x1,//MCBSP_PCR_CLKRM_INPUT,
           MCBSP_PCR_CLKSSTAT_0,
           MCBSP_PCR_DXSTAT_0,
           MCBSP_PCR_FSXP_ACTIVELOW, /* active low trans. frame sync. polarity  */
           MCBSP_PCR_FSRP_ACTIVEHIGH,
           MCBSP_PCR_CLKXP_RISING,  /* trans. clk pol. from rising edge of CLKX */
           MCBSP_PCR_CLKRP_FALLING
           )
}; 
hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); /* McBSP port 0             */
MCBSP_config(hMcbsp0, &mcbspCfg0);
}
/*******************************************************************************************************************
** 函数名称: void SPI_SendByte()				Name:	  void SPI_SendByte()
** 功能描述: 通过SPI接口发送一个字节			Function: send a byte by SPI interface
** 输　  入: INT8U byte: 发送的字节				Input:	  INT8U byte: the byte that will be send
** 输 　 出: 无									Output:	  NULL
********************************************************************************************************************/

void SPI_SendByte(Uint8 byte)
{

	while (!MCBSP_xrdy(hMcbsp0)){}                       
    MCBSP_write(hMcbsp0,byte); 
   // EVMDM642_waitusec(100);  
	while(MCBSP_xempty(hMcbsp0)){}				/* 等待SPIF置位，即等待数据发送完毕 */
										/* wait for SPIF being set, that is, wait for finishing of data being send */
 
}

//hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); /* McBSP port 0             */
//MCBSP_config(hMcbsp0, &mcbspCfg0);
/*******************************************************************************************************************
** 函数名称: INT8U SPI_RecByte()				Name:	  INT8U SPI_RecByte()
** 功能描述: 从SPI接口接收一个字节				Function: receive a byte from SPI interface
** 输　  入: 无									Input:	  NULL
** 输 　 出: 收到的字节							Output:	  the byte that be received
********************************************************************************************************************/
Uint8 SPI_RecByte(void)
{
	
	Uint32 x;
	//if(clk)
	//while (!MCBSP_xrdy(hMcbsp0)){}
	MCBSP_write(hMcbsp0,0xff);
	while (!MCBSP_rrdy(hMcbsp0));
	x = MCBSP_read(hMcbsp0);
	x=x>>24;
	return(x); 							/* 读取收到的字节 read the byte received */
           
  
}