📄 c6416.h
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#ifndef c6416_h
#define c6416_h
#define EMIFAGBLCTL *(int *)0x01800000
#define EMIFACECTL1 *(int *)0x01800004
#define EMIFACECTL0 *(int *)0x01800008
#define EMIFACECTL2 *(int *)0x01800010
#define EMIFACECTL3 *(int *)0x01800014
#define EMIFASDCTL *(int *)0x01800018
#define EMIFASDTIM *(int *)0x0180001C
#define EMIFASDEXT *(int *)0x01800020
#define EMIFACESEC1 *(int *)0x01800044
#define EMIFACESEC0 *(int *)0x01800048
#define EMIFACESEC2 *(int *)0x01800050
#define EMIFACESEC3 *(int *)0x01800054
#define EMIFBGBLCTL *(int *)0x01A80000
#define EMIFBCECTL1 *(int *)0x01A80004
#define EMIFBCECTL0 *(int *)0x01A80008
#define EMIFBCECTL2 *(int *)0x01A80010
#define EMIFBCECTL3 *(int *)0x01A80014
#define EMIFBSDCTL *(int *)0x01A80018
#define EMIFBSDTIM *(int *)0x01A8001C
#define EMIFBSDEXT *(int *)0x01A80020
#define EMIFBCESEC1 *(int *)0x01A80044
#define EMIFBCESEC0 *(int *)0x01A80048
#define EMIFBCESEC2 *(int *)0x01A80050
#define EMIFBCESEC3 *(int *)0x01A80054
#define OPT 0x01A00000 //EDMA channel options parameter register
#define QOPT 0x02000000 //QDMA channel options parameter register
#define SRC 0x01A00004 //EDMA channel source address register
#define QSRC 0x02000004 //QDMA channel source address register
#define CNT 0x01A00008 //EDMA channel transfer count register
#define QCNT 0x02000008 //QDMA channel transfer count register
#define DST 0x01A0000C //EDMA channel destination address register
#define QDST 0x0200000C //QDMA channel destination address register
#define IDX 0x01A00010 //EDMA channel index register
#define QIDX 0x02000010 //QDMA channel index register
#define RLD 0x01A00014 //EDMA channel count reload/link address register
#define QSOPT 0x02000020 //QDMA channel options parameter pseudo register
#define QSSRC 0x02000024 //QDMA channel source address pseudo register
#define QSCNT 0x02000028 //QDMA channel transfer count pseudo register
#define QSDST 0x0200002C //QDMA channel destination address pseudo register
#define QSIDX 0x02000030 //QDMA channel index pseudo register
#define PQSR *(int *)0x01A0FFE0 //Priority queue status register
#define PQAR0 *(int *)0x01A0FFC0 //Priority queue allocation register 0
#define PQAR1 *(int *)0x01A0FFC4 //Priority queue allocation register 1
#define PQAR2 *(int *)0x01A0FFC8 //Priority queue allocation register 2
#define PQAR3 *(int *)0x01A0FFCC //Priority queue allocation register 3
#define CIPRL *(int *)0x01A0FFE4 //EDMA channel interrupt pending low register
#define CIPRH *(int *)0x01A0FFA4 //EDMA channel interrupt pending high register
#define CIERL *(int *)0x01A0FFE8 //EDMA channel interrupt enable low register
#define CIERH *(int *)0x01A0FFA8 //EDMA channel interrupt enable high register
#define CCERL *(int *)0x01A0FFEC //EDMA channel chain enable low register
#define CCERH *(int *)0x01A0FFAC //EDMA channel chain enable high register
#define ERL *(int *)0x01A0FFF0 //EDMA event low register
#define ERH *(int *)0x01A0FFB0 //EDMA event high register
#define EERL *(int *)0x01A0FFF4 //EDMA event enable low register
#define EERH *(int *)0x01A0FFB4 //EDMA event enable high register
#define EPRL *(int *)0x01A0FFDC //EDMA event polarity low register
#define EPRH *(int *)0x01A0FF9C //EDMA event polarity high register
#define ECRL *(int *)0x01A0FFF8 //EDMA event clear low register
#define ECRH *(int *)0x01A0FFB8 //EDMA event clear high register
#define ESRL *(int *)0x01A0FFFC //EDMA event set low register
#define ESRH *(int *)0x01A0FFBC //EDMA event set high register
#define GPEN *(int *)0x01B00000
#define GPDIR *(int *)0x01B00004
#define GPVAL *(int *)0x01B00008
#define IMH *(int*)0x019c0000
#define IML *(int*)0x019c0004
#define EIP *(int*)0x019c0008
volatile cregister unsigned int CSR;
volatile cregister unsigned int IFR;
volatile cregister unsigned int ISR;
volatile cregister unsigned int ICR;
volatile cregister unsigned int IER;
volatile cregister unsigned int ISTP;
#endif /* c6416_h --------- END OF FILE ------------------------------------*/
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