digpll.vhd

曼彻斯特编码

--===========================================
--Digital PLL 
--The output clock of digital Pll is 2M clock
--===========================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity DigPll is
port(
	reset         : in std_logic;
	clkx16        : in std_logic;
	din           : in std_logic;
	clkx2         : out std_logic);
end DigPll;

architecture behav of DigPll is

signal data_temp : std_logic;
signal data_rise : std_logic;
signal clkx2_t   : std_logic;
signal clkx2_r   : std_logic;
signal add       : std_logic;
signal sub       : std_logic;
signal cnt       : std_logic_vector(2 downto 0);

begin
	edge_detect : process(reset,clkx16)
	begin
		if reset = '1' then
			data_temp <= '0';
			data_rise <= '0';
		elsif clkx16'event and clkx16 = '1' then
			data_temp <= din;
			data_rise <= din and (not data_temp);
		end if;
	end process edge_detect;
	
	edge_rise : process(reset,din)
	begin
		if reset = '1' then
			clkx2_t <= '0';
		elsif din'event and din = '1' then
			clkx2_t <= clkx2_r ;
		end if;
	end process edge_rise;
	
	p3 : process(reset,clkx16)
	begin
		if reset = '1' then
			add <= '0';
			sub <= '0';
		elsif clkx16'event and clkx16 = '0' then
			add <= data_rise and (not clkx2_t);
			sub <= data_rise and clkx2_t;
		end if;
	end process p3;
	
	clk_div : process(reset,clkx16)
	begin
		if reset = '1' then
			clkx2_r <= '0';
			cnt     <= "000";
		elsif clkx16'event and clkx16 = '1' then
			clkx2_r <= not cnt(2);
			if add = '1' and sub = '0' then
				cnt <= cnt + "010";
			elsif sub = '1' and add = '0' then
				cnt <= cnt;
			else
				cnt <= cnt + "001";
			end if;
		end if;
	end process clk_div;

	clkx2 <= clkx2_r;
	
end behav;