manchesterdeencoder.tan.qmsg

曼彻斯特编码

{ "Info" "ITDB_TH_RESULT" "data_temp din clkx16 -2.980 ns register " "Info: th for register \"data_temp\" (data pin = \"din\", clock pin = \"clkx16\") is -2.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx16 destination 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clkx16\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkx16 1 CLK PIN_10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx16 } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns data_temp 2 REG LC_X2_Y13_N5 1 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X2_Y13_N5; Fanout = 1; REG Node = 'data_temp'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.998 ns" { clkx16 data_temp } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 data_temp } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 data_temp } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.120 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns din 1 CLK PIN_100 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_100; Fanout = 3; CLK Node = 'din'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { din } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.896 ns) + CELL(0.089 ns) 5.120 ns data_temp 2 REG LC_X2_Y13_N5 1 " "Info: 2: + IC(3.896 ns) + CELL(0.089 ns) = 5.120 ns; Loc. = LC_X2_Y13_N5; Fanout = 1; REG Node = 'data_temp'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "3.985 ns" { din data_temp } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns 23.91 % " "Info: Total cell delay = 1.224 ns ( 23.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.896 ns 76.09 % " "Info: Total interconnect delay = 3.896 ns ( 76.09 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "5.120 ns" { din data_temp } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.120 ns" { din din~out0 data_temp } { 0.000ns 0.000ns 3.896ns } { 0.000ns 1.135ns 0.089ns } } }  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 data_temp } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 data_temp } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "5.120 ns" { din data_temp } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.120 ns" { din din~out0 data_temp } { 0.000ns 0.000ns 3.896ns } { 0.000ns 1.135ns 0.089ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 13 11:00:27 2007 " "Info: Processing ended: Wed Jun 13 11:00:27 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}