manchesterdeencoder.tan.qmsg

曼彻斯特编码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkx16 register add register cnt\[1\] 240.27 MHz 4.162 ns Internal " "Info: Clock \"clkx16\" has Internal fmax of 240.27 MHz between source register \"add\" and destination register \"cnt\[1\]\" (period= 4.162 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.879 ns + Longest register register " "Info: + Longest register to register delay is 1.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add 1 REG LC_X3_Y13_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y13_N2; Fanout = 4; REG Node = 'add'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { add } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.225 ns) 0.659 ns clk_div~1 2 COMB LC_X3_Y13_N6 1 " "Info: 2: + IC(0.434 ns) + CELL(0.225 ns) = 0.659 ns; Loc. = LC_X3_Y13_N6; Fanout = 1; COMB Node = 'clk_div~1'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.659 ns" { add clk_div~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.667 ns) 1.879 ns cnt\[1\] 3 REG LC_X4_Y13_N2 2 " "Info: 3: + IC(0.553 ns) + CELL(0.667 ns) = 1.879 ns; Loc. = LC_X4_Y13_N2; Fanout = 2; REG Node = 'cnt\[1\]'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "1.220 ns" { clk_div~1 cnt[1] } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.892 ns 47.47 % " "Info: Total cell delay = 0.892 ns ( 47.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.987 ns 52.53 % " "Info: Total interconnect delay = 0.987 ns ( 52.53 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "1.879 ns" { add clk_div~1 cnt[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.879 ns" { add clk_div~1 cnt[1] } { 0.000ns 0.434ns 0.553ns } { 0.000ns 0.225ns 0.667ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx16 destination 2.128 ns + Shortest register " "Info: + Shortest clock path from clock \"clkx16\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkx16 1 CLK PIN_10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx16 } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns cnt\[1\] 2 REG LC_X4_Y13_N2 2 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X4_Y13_N2; Fanout = 2; REG Node = 'cnt\[1\]'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.998 ns" { clkx16 cnt[1] } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 cnt[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 cnt[1] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx16 source 2.128 ns - Longest register " "Info: - Longest clock path from clock \"clkx16\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkx16 1 CLK PIN_10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx16 } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns add 2 REG LC_X3_Y13_N2 4 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X3_Y13_N2; Fanout = 4; REG Node = 'add'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.998 ns" { clkx16 add } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 add } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 add } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 cnt[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 cnt[1] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 add } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 add } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 24 -1 0 } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 26 -1 0 } }  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "1.879 ns" { add clk_div~1 cnt[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.879 ns" { add clk_div~1 cnt[1] } { 0.000ns 0.434ns 0.553ns } { 0.000ns 0.225ns 0.667ns } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 cnt[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 cnt[1] } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 add } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 add } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "din " "Info: No valid register-to-register data paths exist for clock \"din\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "data_rise din clkx16 3.299 ns register " "Info: tsu for register \"data_rise\" (data pin = \"din\", clock pin = \"clkx16\") is 3.299 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.398 ns + Longest pin register " "Info: + Longest pin to register delay is 5.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns din 1 CLK PIN_100 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_100; Fanout = 3; CLK Node = 'din'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { din } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.895 ns) + CELL(0.368 ns) 5.398 ns data_rise 2 REG LC_X2_Y13_N6 2 " "Info: 2: + IC(3.895 ns) + CELL(0.368 ns) = 5.398 ns; Loc. = LC_X2_Y13_N6; Fanout = 2; REG Node = 'data_rise'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "4.263 ns" { din data_rise } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.503 ns 27.84 % " "Info: Total cell delay = 1.503 ns ( 27.84 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.895 ns 72.16 % " "Info: Total interconnect delay = 3.895 ns ( 72.16 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "5.398 ns" { din data_rise } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.398 ns" { din din~out0 data_rise } { 0.000ns 0.000ns 3.895ns } { 0.000ns 1.135ns 0.368ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx16 destination 2.128 ns - Shortest register " "Info: - Shortest clock path from clock \"clkx16\" to destination register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkx16 1 CLK PIN_10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx16 } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns data_rise 2 REG LC_X2_Y13_N6 2 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X2_Y13_N6; Fanout = 2; REG Node = 'data_rise'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.998 ns" { clkx16 data_rise } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 data_rise } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 data_rise } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "5.398 ns" { din data_rise } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.398 ns" { din din~out0 data_rise } { 0.000ns 0.000ns 3.895ns } { 0.000ns 1.135ns 0.368ns } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 data_rise } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 data_rise } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkx16 clkx2 clkx2_r 4.914 ns register " "Info: tco from clock \"clkx16\" to destination pin \"clkx2\" through register \"clkx2_r\" is 4.914 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkx16 source 2.128 ns + Longest register " "Info: + Longest clock path from clock \"clkx16\" to source register is 2.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clkx16 1 CLK PIN_10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx16 } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.547 ns) 2.128 ns clkx2_r 2 REG LC_X2_Y13_N2 2 " "Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X2_Y13_N2; Fanout = 2; REG Node = 'clkx2_r'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.998 ns" { clkx16 clkx2_r } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 78.81 % " "Info: Total cell delay = 1.677 ns ( 78.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.451 ns 21.19 % " "Info: Total interconnect delay = 0.451 ns ( 21.19 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 clkx2_r } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 clkx2_r } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.613 ns + Longest register pin " "Info: + Longest register to pin delay is 2.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkx2_r 1 REG LC_X2_Y13_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N2; Fanout = 2; REG Node = 'clkx2_r'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx2_r } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.991 ns) + CELL(1.622 ns) 2.613 ns clkx2 2 PIN PIN_99 0 " "Info: 2: + IC(0.991 ns) + CELL(1.622 ns) = 2.613 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'clkx2'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.613 ns" { clkx2_r clkx2 } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 62.07 % " "Info: Total cell delay = 1.622 ns ( 62.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns 37.93 % " "Info: Total interconnect delay = 0.991 ns ( 37.93 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.613 ns" { clkx2_r clkx2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.613 ns" { clkx2_r clkx2 } { 0.000ns 0.991ns } { 0.000ns 1.622ns } } }  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.128 ns" { clkx16 clkx2_r } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.128 ns" { clkx16 clkx16~out0 clkx2_r } { 0.000ns 0.000ns 0.451ns } { 0.000ns 1.130ns 0.547ns } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "2.613 ns" { clkx2_r clkx2 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.613 ns" { clkx2_r clkx2 } { 0.000ns 0.991ns } { 0.000ns 1.622ns } } }  } 0}