manchesterdeencoder.fit.qmsg

曼彻斯特编码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 13 11:00:16 2007 " "Info: Processing started: Wed Jun 13 11:00:16 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ManchesterDeEncoder -c ManchesterDeEncoder " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ManchesterDeEncoder -c ManchesterDeEncoder" {  } {  } 0}
{ "Info" "IMPP_MPP_AVAILABLE_IO_STANDARD_IN_DEVICE" "EP1C3T100C6 " "Info: Auto device selection -- successful I/O standard check for EP1C3T100C6" {  } {  } 0}
{ "Info" "IMPP_MPP_AVAILABLE_PCI_IO_IN_DEVICE" "EP1C3T100C6 " "Info: Auto device selection -- successful PCI I/O clamp diode check for EP1C3T100C6" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "ManchesterDeEncoder EP1C3T100C6 " "Info: Automatically selected device EP1C3T100C6 for design ManchesterDeEncoder" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " {  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "4 4 " "Info: No exact pin location assignment(s) for 4 pins of 4 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clkx2 " "Info: Pin clkx2 not assigned to an exact location on the device" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkx2" } } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx2 } "NODE_NAME" } "" } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" "" { clkx2 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clkx16 " "Info: Pin clkx16 not assigned to an exact location on the device" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkx16" } } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { clkx16 } "NODE_NAME" } "" } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" "" { clkx16 } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "reset " "Info: Pin reset not assigned to an exact location on the device" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { reset } "NODE_NAME" } "" } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" "" { reset } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din " "Info: Pin din not assigned to an exact location on the device" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 14 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "din" } } } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { din } "NODE_NAME" } "" } } { "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.fld" "" "" { din } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkx16 Global clock in PIN 10 " "Info: Automatically promoted signal \"clkx16\" to use Global clock in PIN 10" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 13 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reset Global clock in PIN 66 " "Info: Automatically promoted signal \"reset\" to use Global clock in PIN 66" {  } { { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 12 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.30 1 1 0 " "Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 1 16 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  16 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.744 ns register register " "Info: Estimated most critical path is register to register delay of 1.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sub 1 REG LAB_X3_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y13; Fanout = 4; REG Node = 'sub'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "" { sub } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 25 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.116 ns) + CELL(0.454 ns) 0.570 ns clk_div~1 2 COMB LAB_X3_Y13 1 " "Info: 2: + IC(0.116 ns) + CELL(0.454 ns) = 0.570 ns; Loc. = LAB_X3_Y13; Fanout = 1; COMB Node = 'clk_div~1'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "0.570 ns" { sub clk_div~1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.507 ns) + CELL(0.667 ns) 1.744 ns cnt\[1\] 3 REG LAB_X4_Y13 2 " "Info: 3: + IC(0.507 ns) + CELL(0.667 ns) = 1.744 ns; Loc. = LAB_X4_Y13; Fanout = 2; REG Node = 'cnt\[1\]'" {  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "1.174 ns" { clk_div~1 cnt[1] } "NODE_NAME" } "" } } { "DigPll.vhd" "" { Text "C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.121 ns 64.28 % " "Info: Total cell delay = 1.121 ns ( 64.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.623 ns 35.72 % " "Info: Total interconnect delay = 0.623 ns ( 35.72 % )" {  } {  } 0}  } { { "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" "" { Report "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder_cmp.qrpt" Compiler "ManchesterDeEncoder" "UNKNOWN" "V1" "C:/altera/qdesigns50/works/ManchesterDeEncoder/db/ManchesterDeEncoder.quartus_db" { Floorplan "C:/altera/qdesigns50/works/ManchesterDeEncoder/" "" "1.744 ns" { sub clk_div~1 cnt[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 13 11:00:22 2007 " "Info: Processing ended: Wed Jun 13 11:00:22 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}