manchesterencoder.vhd

曼彻斯特编码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ManchesterEncoder is
port(
	reset       : in   std_logic;
	clkx16      : in   std_logic;
--write control signal 
	wr          : in   std_logic;
--appoint the word type
	cmnd        : in   std_logic;
--data need to be encoded
	din         : in   std_logic_vector(15 downto 0);
--encoder ready signal 	
	txrdyn      : out  std_logic;
--ManchesterII code output	
	txdata      : out  std_logic;
	txdata_n    : out  std_logic
	);
end ManchesterEncoder;

architecture behav of ManchesterEncoder is

component ClockGenEn is
port(
	reset    : in  std_logic;
	clkx16   : in  std_logic;
	clkx1    : out std_logic;
	clkx2    : out std_logic);
end component ClockGenEn;

signal clkx1              : std_logic;
signal clkx2              : std_logic;
--synchronization bits encode start signal
signal sync_start         : std_logic;
--synchornization bits shift counter
signal sync_count         : std_logic_vector(2 downto 0);
--synchornization bits register(six bits and 2M clock)
signal sync_shift_temp    : std_logic_vector(5 downto 0);
--synchornization bits output enable signal
signal sync_out_en        : std_logic;
--synchornization bits output register 
signal txdata_s           : std_logic;

--encode register
signal data_shift_temp    : std_logic_vector(15 downto 0);
--encode shift counter
signal shift_cnt          : std_logic_vector(4 downto 0);
--code data output register
signal data_shift_out     : std_logic;

--odd parity register
signal parity             : std_logic;

--state machine definition
type state_type is(idle,sync,encode);
signal encode_state      : state_type;

begin

	I1 : ClockGenEn port map(
							reset    => reset,
							clkx16   => clkx16,
							clkx1    => clkx1,
							clkx2    => clkx2);

--synchornization bits generator
	sync_generator : process(reset,clkx2)
	begin
		if reset = '1' then
			sync_count      <= "000";
			sync_shift_temp <= "000000";
			txdata_s        <= '0';
			sync_out_en     <= '0';
		elsif clkx2'event and clkx2 = '1' then
			if sync_start = '1' then
				if sync_count = "000" then
--If the data need to be encoded for status word, then the sync bits are "111000"
--Otherswise ,the value is "000111"
					if cmnd = '1' then
						sync_shift_temp       <= "111000";
					elsif cmnd = '0' then
						sync_shift_temp       <= "000111";
					end if;
					sync_count         <= sync_count + "001";
--Begin to shift
				elsif sync_count > "000" then
					txdata_s           <= sync_shift_temp(5);
					sync_shift_temp    <= sync_shift_temp(4 downto 0) & '0'; 
					sync_count         <= sync_count + "001";	
--Generate the synchornization bits output enable signal
					if sync_count >= "001" then
						sync_out_en    <= '1';
					end if;
				end if; 
--sync generator not work condition
			else
				sync_out_en     <= '0';
				txdata_s        <= '0';
				sync_count      <= "000";
			end if;
		end if;
	end process sync_generator;

--output code 	
	output_process : process(clkx2,clkx1,encode_state,sync_out_en,txdata_s,data_shift_out,data_shift_temp(15)
								  ,shift_cnt,parity)
	begin		
		if clkx2'event and clkx2 = '1' then
			if encode_state = sync and sync_out_en = '1' then
				txdata   <= txdata_s;
				txdata_n <= not txdata_s;
			elsif encode_state = encode  and shift_cnt < "10000" then
				txdata_n <= not (data_shift_temp(15) xor clkx1);
				txdata   <= data_shift_temp(15) xor clkx1;
			elsif encode_state = encode and shift_cnt = "10000" then
				txdata_n <= not (data_shift_out xor clkx1);
				txdata   <= data_shift_out xor clkx1;
			else
				txdata_n <= not ('0' xor clkx1);
				txdata   <= '0' xor clkx1;
			end if; 
		end if;
	end process output_process;

--encoder ready signal ,low is valid
	txrdyn <= '1' when encode_state = idle else
	          '0';

--state control machine	
	state_machine : process(reset,clkx1)
	begin
		if reset = '1' then
			encode_state    <= idle;
			sync_start      <= '0';
			data_shift_temp <= X"0000";
		elsif clkx1'event and clkx1 = '1' then
			case encode_state is
			--if wr signal is high ,then state machine turn to work in 'sync' 
			--otherwise it will still work in 'idle'
				when idle   =>	if wr = '1' then
									sync_start      <= '1';
									data_shift_temp <= din;
									encode_state    <= sync;
								end if;
								shift_cnt           <= "00000";
								parity              <= '1';
			--if sync generator finished ,then turn to encode 
				when sync   =>	if sync_count = "110" or sync_count = "111" then
									sync_start    <= '0';
									encode_state  <= encode;
								end if;
				when encode =>	if shift_cnt >= "00000" and shift_cnt <= "01111" then
									data_shift_temp <= data_shift_temp(14 downto 0) & '0';
									shift_cnt       <= shift_cnt + "00001";
								--odd praity
									parity          <= parity xor data_shift_temp(15);
									if shift_cnt = "01111" then
										data_shift_out <= parity;
									end if;
								elsif shift_cnt = "10000" then
									encode_state      <= idle;
								end if;
				when others =>	encode_state          <= idle;
			end case;
		end if;
	end process state_machine;
	
end behav;