manchesterdeencoder.tan.rpt

曼彻斯特编码

+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tsu                                                             ;
+-------+--------------+------------+------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To        ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A   ; None         ; 3.299 ns   ; din  ; data_rise ; clkx16   ;
; N/A   ; None         ; 3.021 ns   ; din  ; data_temp ; clkx16   ;
+-------+--------------+------------+------+-----------+----------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+---------+-------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To    ; From Clock ;
+-------+--------------+------------+---------+-------+------------+
; N/A   ; None         ; 4.914 ns   ; clkx2_r ; clkx2 ; clkx16     ;
+-------+--------------+------------+---------+-------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -2.980 ns ; din  ; data_temp ; clkx16   ;
; N/A           ; None        ; -3.258 ns ; din  ; data_rise ; clkx16   ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Jun 13 11:00:27 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ManchesterDeEncoder -c ManchesterDeEncoder --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkx16" is an undefined clock
    Info: Assuming node "din" is an undefined clock
Info: Clock "clkx16" has Internal fmax of 240.27 MHz between source register "add" and destination register "cnt[1]" (period= 4.162 ns)
    Info: + Longest register to register delay is 1.879 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y13_N2; Fanout = 4; REG Node = 'add'
        Info: 2: + IC(0.434 ns) + CELL(0.225 ns) = 0.659 ns; Loc. = LC_X3_Y13_N6; Fanout = 1; COMB Node = 'clk_div~1'
        Info: 3: + IC(0.553 ns) + CELL(0.667 ns) = 1.879 ns; Loc. = LC_X4_Y13_N2; Fanout = 2; REG Node = 'cnt[1]'
        Info: Total cell delay = 0.892 ns ( 47.47 % )
        Info: Total interconnect delay = 0.987 ns ( 52.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clkx16" to destination register is 2.128 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'
            Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X4_Y13_N2; Fanout = 2; REG Node = 'cnt[1]'
            Info: Total cell delay = 1.677 ns ( 78.81 % )
            Info: Total interconnect delay = 0.451 ns ( 21.19 % )
        Info: - Longest clock path from clock "clkx16" to source register is 2.128 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'
            Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X3_Y13_N2; Fanout = 4; REG Node = 'add'
            Info: Total cell delay = 1.677 ns ( 78.81 % )
            Info: Total interconnect delay = 0.451 ns ( 21.19 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: No valid register-to-register data paths exist for clock "din"
Info: tsu for register "data_rise" (data pin = "din", clock pin = "clkx16") is 3.299 ns
    Info: + Longest pin to register delay is 5.398 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_100; Fanout = 3; CLK Node = 'din'
        Info: 2: + IC(3.895 ns) + CELL(0.368 ns) = 5.398 ns; Loc. = LC_X2_Y13_N6; Fanout = 2; REG Node = 'data_rise'
        Info: Total cell delay = 1.503 ns ( 27.84 % )
        Info: Total interconnect delay = 3.895 ns ( 72.16 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "clkx16" to destination register is 2.128 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'
        Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X2_Y13_N6; Fanout = 2; REG Node = 'data_rise'
        Info: Total cell delay = 1.677 ns ( 78.81 % )
        Info: Total interconnect delay = 0.451 ns ( 21.19 % )
Info: tco from clock "clkx16" to destination pin "clkx2" through register "clkx2_r" is 4.914 ns
    Info: + Longest clock path from clock "clkx16" to source register is 2.128 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'
        Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X2_Y13_N2; Fanout = 2; REG Node = 'clkx2_r'
        Info: Total cell delay = 1.677 ns ( 78.81 % )
        Info: Total interconnect delay = 0.451 ns ( 21.19 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.613 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y13_N2; Fanout = 2; REG Node = 'clkx2_r'
        Info: 2: + IC(0.991 ns) + CELL(1.622 ns) = 2.613 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'clkx2'
        Info: Total cell delay = 1.622 ns ( 62.07 % )
        Info: Total interconnect delay = 0.991 ns ( 37.93 % )
Info: th for register "data_temp" (data pin = "din", clock pin = "clkx16") is -2.980 ns
    Info: + Longest clock path from clock "clkx16" to destination register is 2.128 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'clkx16'
        Info: 2: + IC(0.451 ns) + CELL(0.547 ns) = 2.128 ns; Loc. = LC_X2_Y13_N5; Fanout = 1; REG Node = 'data_temp'
        Info: Total cell delay = 1.677 ns ( 78.81 % )
        Info: Total interconnect delay = 0.451 ns ( 21.19 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.120 ns
        Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_100; Fanout = 3; CLK Node = 'din'
        Info: 2: + IC(3.896 ns) + CELL(0.089 ns) = 5.120 ns; Loc. = LC_X2_Y13_N5; Fanout = 1; REG Node = 'data_temp'
        Info: Total cell delay = 1.224 ns ( 23.91 % )
        Info: Total interconnect delay = 3.896 ns ( 76.09 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Jun 13 11:00:27 2007
    Info: Elapsed time: 00:00:01