clockgenen.vhd

来自「曼彻斯特编码」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ClockGenEn is
port(
	clkx16         : in std_logic;
	reset          : in std_logic;
	clkx1          : out std_logic;
	clkx2          : out std_logic);
end ClockGenEn;

architecture behav of ClockGenEn is

signal clk_cnt     : std_logic_vector(3 downto 0);
 
begin
	process(reset,clkx16)
	begin
		if reset = '1' then
			clk_cnt <= "0000";
		elsif clkx16'event and clkx16 = '1' then
			clk_cnt <= clk_cnt + "0001";
			clkx2   <= not clk_cnt(2);
			clkx1   <= not clk_cnt(3);
		end if;
	end process;
end behav;