clockgenerator.vhd

曼彻斯特编码

--=============================================================
--Clock Generator
--The generated clock include: decode clock(1M)
--							   transmit clock(1M)
--							   synchornize bits detect clock(2M)
--=============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ClockGenerator is
port(
	clkx16                : in std_logic;
	reset                 : in std_logic;
	decode_start          : in std_logic;  --decode clock generator enable signal
	transmit_start        : in std_logic;  --transmit clock generator enable signal
	pll_clkx2             : in std_logic;
	det_clkx2             : out std_logic; --detect clock
	tra_clkx1             : out std_logic; --transmit clock
	pll_clkx1             : out std_logic);--decode clock
end ClockGenerator;

architecture behav of ClockGenerator is
--detect clock counter
signal detect_clock_cnt         : std_logic_vector(2 downto 0);
--detect clock output register
signal det_clkx2_r              : std_logic;
--transmit clock counter
signal transmit_clock_cnt       : std_logic_vector(3 downto 0);
--transmit clock output register
signal tra_clkx1_r              : std_logic;
--decode clock output register
signal pll_clkx1_r              : std_logic;

begin

--synchornize bits detect clock generator
	detect_clock : process(reset,clkx16)
	begin
		if reset = '1' then
			detect_clock_cnt <= "000";
		elsif clkx16'event and clkx16 = '1' then
			detect_clock_cnt <= detect_clock_cnt + "001";
			det_clkx2_r      <= not detect_clock_cnt(2);
		end if;
	end process detect_clock;

--transmit clock generator
	transmit_clock : process(reset,transmit_start,clkx16)
	begin
		if reset = '1' or transmit_start = '1' then
			transmit_clock_cnt <= "0000";
			tra_clkx1_r		   <= '0';
		elsif clkx16'event and clkx16 = '1' then
			transmit_clock_cnt <= transmit_clock_cnt + "0001";
			tra_clkx1_r        <= not transmit_clock_cnt(3);
		end if;
	end process transmit_clock;

--decode clock generator
	decoder_clock : process(reset,decode_start,pll_clkx2)
	begin
		if reset = '1' or decode_start = '1' then
			pll_clkx1_r <= '0';
		elsif pll_clkx2'event and pll_clkx2 = '1' then
			pll_clkx1_r <= not pll_clkx1_r;
		end if;
	end process decoder_clock;

--detect clock output	
	det_clkx2 <= det_clkx2_r;
--transmit clock output
	tra_clkx1 <= tra_clkx1_r;
--decode clock output
	pll_clkx1 <= pll_clkx1_r;
	
end behav;