manchesterdeencoder.map.rpt

曼彻斯特编码

; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On                  ;
+--------------------------------------------------------------------+--------------+---------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                           ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                              ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------+
; DigPll.vhd                       ; yes             ; User VHDL File  ; C:/altera/qdesigns50/works/ManchesterDeEncoder/DigPll.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 12        ;
; Total combinational functions   ; 7         ;
;     -- Total 4-input functions  ; 2         ;
;     -- Total 3-input functions  ; 0         ;
;     -- Total 2-input functions  ; 5         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 9         ;
; I/O pins                        ; 4         ;
; Maximum fan-out node            ; reset     ;
; Maximum fan-out                 ; 9         ;
; Total fan-out                   ; 45        ;
; Average fan-out                 ; 2.81      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |DigPll                    ; 12 (12)     ; 9            ; 0           ; 4    ; 0            ; 3 (3)        ; 5 (5)             ; 4 (4)            ; 0 (0)           ; |DigPll             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 9     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |DigPll|cnt[2]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/qdesigns50/works/ManchesterDeEncoder/ManchesterDeEncoder.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Wed Jun 13 11:00:10 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ManchesterDeEncoder -c ManchesterDeEncoder
Info: Found 2 design units, including 1 entities, in source file ManchesterDecoder.vhd
    Info: Found design unit 1: ManchesterDecoder-behav
    Info: Found entity 1: ManchesterDecoder
Info: Found 2 design units, including 1 entities, in source file DigPll.vhd
    Info: Found design unit 1: DigPll-behav
    Info: Found entity 1: DigPll
Info: Found 2 design units, including 1 entities, in source file ClockGenerator.vhd
    Info: Found design unit 1: ClockGenerator-behav
    Info: Found entity 1: ClockGenerator
Info: Found 2 design units, including 1 entities, in source file ClockGenEn.vhd
    Info: Found design unit 1: ClockGenEn-behav
    Info: Found entity 1: ClockGenEn
Info: Elaborating entity "DigPll" for the top level hierarchy
Info: Implemented 16 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 12 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Wed Jun 13 11:00:14 2007
    Info: Elapsed time: 00:00:05