cache_config.c

ADI-BF533 DSP cache的配置代码

#include <def_LPBlackfin.h>
#include <cplb.h>

// function declare
extern void Config_D_Cache(unsigned int *cplb_addr, unsigned int *cplb_data, int cplb_cnt, int banks);
extern void Config_I_Cache(unsigned int *cblb_addr, unsigned int *cplb_data, int cplb_cnt, int no_lru, int *W_Lock);



// Number of entries for DCPLB & ICPLB descriptors
#define DCPLB_CNT 10
#define ICPLB_CNT 9

 

// Entries for the DCPLBx_ADDR
unsigned int D_cplb_addrs[DCPLB_CNT] =
	{
		0xff800000,	
		0xff900000, 
		0x00000000,	
		0x00400000,	
		0x00800000, 
		0x00C00000, 
		0x01000000,	
		0x01400000,	
		0x01800000, 
		0x01C00000 
	};

			

// Entries for the DCPLBx_DATA
unsigned int D_cplb_data[DCPLB_CNT] =
	{
		PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT,//0x2001f,
		PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT,//0x2001f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f,
		PAGE_SIZE_4MB | CPLB_DDOCACHE,//0x3D01f
	};
		

// Entries for the ICPLBx_ADDR
unsigned int I_cplb_addrs[ICPLB_CNT] =
	{
		0xFFA00000, 
		0x00000000, 
		0x00400000, 
		0x00800000, 
		0x00C00000, 
		0x01000000, 
		0x01400000, 
		0x01800000, 
		0x01C00000
	};

			

// Entries for the ICPLBx_DATA		
unsigned int I_cplb_data[ICPLB_CNT] =
	{
		PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT,//0x00020003,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005,
		PAGE_SIZE_4MB | CPLB_IDOCACHE,//0x00031005
	};

			
// Lock Control for the ICache 
//	1: Lock the way		
//	0: Don't Lock 			

int Lock_Control[4] =
	{
		0,
		1,
		1,
		1
	};
	

	

	
	
// 1 Only one bank-A enabled as Cache 
// 2 Both the banks enabled as Cache
#define D_BANK_CNT 2

// Select the LRU Policy
#define DISABLE_LRU 0
	
void Config_Cache()
{

	Config_D_Cache(D_cplb_addrs, D_cplb_data, DCPLB_CNT, D_BANK_CNT);

	Config_I_Cache(I_cplb_addrs, I_cplb_data, ICPLB_CNT, DISABLE_LRU, Lock_Control);
}