pll_sdram.asm

ADI-BF533 DSP cache的配置代码

/*****************************************************************************************************************

(C) Copyright 2003 - Analog Devices, Inc.  All rights reserved.

File Name:		startup.asm

Date Modified:	3/5/03		LB		Rev 0.3

			0.0  		Original Release
				
Software:       VisualDSP++3.1

Hardware:		ADSP-BF533 EZKIT Lite

Purpose:		Generic Startup file				
************************************************************************************************/

#include <defBF533.h>
#include "PLL_SDRAM.h"

.section l1_code
_START:

// Initialize System Configuration Register
	
	r1 = SYSCFG_VALUE;
	SYSCFG = r1;

// Reconfigure PLL_CTL Register

#if defined(PLL_MSEL)  || defined(PLL_D)

	#ifdef PLL_LOCK_COUNT
		p0.l = lo(PLL_LOCKCNT);
		p0.h = hi(PLL_LOCKCNT);		
		r0.l = lo(PLL_LOCK_COUNT);
		r0.h = hi((PLL_LOCK_COUNT);
		w[p0] = r0;	
	#endif	//PLL_LOCK_COUNT
	
	p0.l = lo(PLL_CTL);
	p0.h = hi(PLL_CTL);
	r1 = w[p0](z);
	r2 = r1;  
	r0 = 0(z);
		
	#ifdef PLL_D
		bitclr(r1,0);
		r0.l = (PLL_D & 0x1);
		r1 = r1 | r0;
	#endif // PLL_D
	
	#ifdef PLL_MSEL
		r0.l = ~(0x3f << 9);
		r1 = r1 & r0;
		r0.l = ((PLL_MSEL & 0x3f) << 9);
		r1 = r1 | r0;
	#endif // PLL_MSEL

 	cc = r1 == r2;       // check if PLL_CTL changed
 	if cc jump skip_pll; // skip the PLL_CTL update


 	p1.l = lo(SIC_IWR);  // enable PLL Wakeup Interrupt
	p1.h = hi(SIC_IWR);
	r0 = [p1];			
	bitset(r0,0);	  
	[p1] = r0;
	
 	w[p0] = r1;          // Apply PLL_CTL changes.
	ssync;
 	
	cli r2; // disable interrupts 15-5
 	idle;	// wait for Loop_count expired wake up
 	sti r2; // enable interrupts 15-5
	
 	skip_pll: nop;

#endif //(PLL_MSEL | PLL_D)
//-------------------------------------
	
// Reconfigure PLL_DIV Register
// Can be done on the fly

#if defined(PLL_CSEL) | defined(PLL_SSEL)
	p0.l = lo(PLL_DIV);
	p0.h = hi(PLL_DIV);
	r1 = w[p0](z);
	r0 = 0(z);
	
	#ifdef PLL_CSEL
		r0.l = ~(0x3<<4);
		r1 = r1 & r0;
		r0.l = ((PLL_CSEL & 0x3)<<4);
		r1 = r1 | r0;
	#endif // PLL_CSEL
	
	#ifdef PLL_SSEL
		r0.l = ~(0xf);
		r1 = r1 & r0;
		r0.l = (PLL_SSEL & 0xf);
		r1 = r1 | r0;
	#endif // PLL_SSEL
	
	w[p0] =r1;
	ssync;
#endif //(PLL_CSEL | PLL_SSEL)
//--------------------------------------


#ifdef EN_SDRAM
	// Check if already enabled
	p0.l = lo(EBIU_SDSTAT);
	p0.h = hi(EBIU_SDSTAT);
	r0 = [p0];
	cc = bittst(r0, bitpos(SDRS));  // SDRS
	if !cc jump skip_sdram_enable;
	
	//SDRAM Refresh Rate Control Register
	P0.L = lo(EBIU_SDRRC);
	P0.H = hi(EBIU_SDRRC);
	R0.L = 0x0817;								
	W[P0] = R0.L;

	//SDRAM Memory Bank Control Register
	P0.L = lo(EBIU_SDBCTL);			
	P0.H = hi(EBIU_SDBCTL);					
	R0.L = 0x0017;													
	W[P0] = R0.L;

	//SDRAM Memory Global Control Register	
	P0.L = lo(EBIU_SDGCTL);
	P0.H = hi(EBIU_SDGCTL);
	R0.L = 0x998d;
	R0.H = 0x0091;
	[P0] = R0;	
	ssync;	
	
	skip_sdram_enable: nop;
#endif // EN_SDRAM


	rti;		
		



_START.end: nop;