config_d_cache.c

ADI-BF533 DSP cache的配置代码

#include <cdefbf533.h>
#include <defbf533.h>


/****************************************************************/
/*	Routine for Configuring the DCPLBs and Enabling Data Cache	*/
/*																*/
/*	Parameters:													*/
/*																*/
/*	cplb_addr : Pointer to the Page Table for DCPLB_ADDR		*/
/*	cplb_data : Pointer to the Page Table for DCPLB_DATA		*/
/*	cplb_cnt  : Number of CPLB entries to be configured			*/
/*	banks	  : Number of data banks to be enabled as DCACHE	*/
/*																*/
/*									Initial Version				*/
/*																*/
/****************************************************************/
void Config_D_Cache(unsigned int *cplb_addr, unsigned int *cplb_data, int cplb_cnt, int banks)
{		
		int temp;
		
		
		// Disable the DCPLBs
		// Disable the D_Cache
		// Invalidate Cache
		*pDMEM_CONTROL = 0x1;
		asm("CSYNC;");
        
		// Configure the CPLB_ADDR Entries
        for(temp = 0; temp<cplb_cnt; temp++)
        {
        	(unsigned int)*(pDCPLB_ADDR0 + temp) = *(cplb_addr + temp);
        	asm("CSYNC;");
        }
		
        // Configure DCPLB_DATA entries
        for(temp = 0; temp<cplb_cnt; temp++)
        {
        	*(pDCPLB_DATA0 + temp) = *(cplb_data + temp);
        	asm("CSYNC;");
        }
		
        // Enable Cache, Enable CPLBs
        if (banks == 1)
        {
       		// Only one bank-A enabled as Cache
       		*pDMEM_CONTROL = 0x100B;
       		asm("ssync;");
        }
        else
        {
        	if (banks == 2)
        	{
        		// Both the banks enabled as Cache
        		*pDMEM_CONTROL = 0x100F;
        		asm("ssync;");
        	}
        }
        
} //Config_D_Cache