config_i_cache.c

ADI-BF533 DSP cache的配置代码

#include <cdefbf533.h>
#include <defbf533.h>

/****************************************************************/
/*	Routine for Configuring the ICPLBs and Enabling Instr Cache	*/
/*																*/
/*	Parameters:													*/
/*																*/
/*	cplb_addr : Pointer to the Page Table for ICPLB_ADDR		*/
/*	cplb_data : Pointer to the Page Table for ICPLB_DATA		*/
/*	cplb_cnt  : Number of CPLB entries to be configured			*/
/*	no_lru	  : The modified LRU policy disabled if (no_lru==1) */
/*	W_Lock	  : Way-n will be locked if ( *(W_Lock + n) == 1 )	*/
/*																*/
/*																*/
/*									Initial Version				*/
/*																*/
/****************************************************************/

void Config_I_Cache(unsigned int *cblb_addr, unsigned int *cplb_data, int cplb_cnt, int no_lru, int *W_Lock)
{
	int temp;
	unsigned int imem_cntrl;
	
	// CPLBs/Cache disabled 
	// Invalidate Cache	
	*pIMEM_CONTROL = 0x1;
	asm("CSYNC;");
	
	// Configure the ICPLB_ADDR [n]
	for (temp=0; temp<cplb_cnt; temp++)
	{
		(unsigned int)*(pICPLB_ADDR0 + temp) = *(cblb_addr + temp);
        asm("CSYNC;");
        
	}
	
	// Configure the ICPLB_DATA [n]
	for(temp = 0; temp<cplb_cnt; temp++)
    {
    	*(pICPLB_DATA0 + temp) = *(cplb_data + temp);
    	asm("CSYNC;");
    }
	
    // Enable the ICache and ICPLBs
    imem_cntrl = 0x7;
    
    // Select the LRU Policy
    if (no_lru == 1)
    {
    	// Disable the Modified LRU policy
    	imem_cntrl |= 0x2000;
    }
    
    // Select the Way Locking
    if (*W_Lock == 1)
    {
    	// Lock Way 0
    	imem_cntrl |= 0x8;
    }
    if (*(W_Lock+1) == 1)
    {
    	// Lock Way 1
    	imem_cntrl |= 0x10;
    }
    if (*(W_Lock+2) == 1)
    {
    	// Lock Way 1
    	imem_cntrl |= 0x20;
    }
    if (*(W_Lock+3) == 1)
    {
    	// Lock Way 1
    	imem_cntrl |= 0x40;
    }
    
	// Enable the Instruction Cache and CPLBs
	*pIMEM_CONTROL = imem_cntrl;
	asm("SSYNC;");
	
} // Config_I_Cache