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📄 bf533 flags c.ldf

📁 ADI-BF533 DSP的启动初始化配置源代码
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** 0xFF807FDF-0xFF807FFF used by boot-loader for 0.2 silicon. 
** 0xFF807FEF-0xFF807FFF used by boot-loader for 0.3 and later silicon. 
** Does not impact use as heap or cache.
*/
MEM_L1_DATA_A_CACHE        {	/* L1 Data A SRAM/Cache - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF804000) END(0xFF807FFF)
}
#ifdef IDDE_ARGS
MEM_ARGV        {
#define ARGV_START 0xFF803F00
	TYPE(RAM) WIDTH(8)
	START(0xFF803F00) END(0xFF803FFF)
}
MEM_L1_DATA_A        {	/* L1 Data A SRAM - most of 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF800000) END(0xFF803EFF)
}
#else
MEM_L1_DATA_A        {	/* L1 Data A SRAM - 16K */
	TYPE(RAM) WIDTH(8)
	START(0xFF800000) END(0xFF803FFF)
}
#endif
MEM_ASYNC3     {	/* Async Bank 3 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20300000) END(0x203FFFFF)
}
MEM_ASYNC2     {	/* Async Bank 2 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20200000) END(0x202FFFFF)
}
MEM_ASYNC1     {	/* Async Bank 1 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20100000) END(0x201FFFFF)
}
MEM_ASYNC0     {	/* Async Bank 0 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20000000) END(0x200FFFFF)
}

#ifdef PARTITION_EZKIT_SDRAM
MEM_SDRAM0_BANK0  { /* SDRAM: Ext Bank0, Int Bank0: 8MB */
    /* Used for heap */
    TYPE(RAM) WIDTH(8)
    START(0x00000004) END(0x007FFFFF)
}
MEM_SDRAM0_BANK1  { /* SDRAM: Ext Bank0, Int Bank1: 8MB */
    /* Used for data */
    TYPE(RAM) WIDTH(8)
    START(0x00800000) END(0x00FFFFFF)
}
MEM_SDRAM0_BANK2  { /* SDRAM: Ext Bank0, Int Bank2: 8MB */
    /* Used for data/bsz */
    TYPE(RAM) WIDTH(8)
    START(0x01000000) END(0x017FFFFF)
}
MEM_SDRAM0_BANK3  { /* SDRAM: Ext Bank0, Int Bank3: 8MB */
    /* Used for program */
    TYPE(RAM) WIDTH(8)
    START(0x01800000) END(0x01FFFFFF)
}
#else
/* Claim some of SDRAM Bank 0 for heap */
/* since it needs a separate section */

MEM_SDRAM0     {	/* SDRAM Bank 0 - 16MB-128M */
	TYPE(RAM) WIDTH(8)
	START(0x00004000) END(0x07FFFFFF)
}
MEM_SDRAM0_HEAP     {	/* Claim some for ext heap - 16K */
	TYPE(RAM) WIDTH(8)
	START(0x00000004) END(0x00003FFF)
}
#endif
}

PROCESSOR P0
{
    OUTPUT( $COMMAND_LINE_OUTPUT_FILE )

	/* Following address must match start of MEM_PROGRAM */
	RESOLVE(start,0xffa00000)
#ifdef IDDE_ARGS
	RESOLVE(___argv_string, ARGV_START)
#endif
	KEEP(start,_main)

  SECTIONS
  {

#if defined(__WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES) /* { */
    /* Workaround for hardware errata 05-00-0189 - 
    ** "Speculative (and fetches made at boundary of reserved memory
    ** space) for instruction or data fetches may cause false
    ** protection exceptions".
    ** 
    ** Done by avoiding use of 76 bytes from at the end of blocks
    ** that are adjacent to reserved memory. Workaround is enabled 
    ** for appropriate silicon revisions (-si-revision switch).
    */
    RESERVE(___wab0=0xFFB00FFF - 75,___l0=76, 1) /* scratchpad */
#  if INSTR_CACHE
    RESERVE(___wab1=0xFFA0FFFF - 75,___l1=76) /* l1 instr sram */
#  else
    RESERVE(___wab2=0xFFA13FFF - 75,___l2=76, 1) /* l1 instr sram/cache */ 
#  endif /* INSTR_CACHE } */
#  if DATAB_CACHE 
    RESERVE(___wab3=0xFF903FFF - 75,___l3=76) /* data B sram */
#  else
    RESERVE(___wab4=0xFF907FFF - 75,___l4=76, 1) /* data B sram/cache */
#  endif
#  if DATAA_CACHE 
    RESERVE(___wab5=0xFF803FFF - 75,___l5=76) /* data A sram */
#  else
    RESERVE(___wab6=0xFF807FFF - 75,___l6=76, 1) /* data A sram/cache */
#  endif
    RESERVE(___wab7=0x203FFFFF - 75,___l7=76, 1) /* async bank 3 */
#  if defined(PARTITION_EZKIT_SDRAM) /* { */
    RESERVE(___wab8=0x17FFFFF - 75,___l8=76)  /*EZ-Kit sdram */
#  elif defined(USE_CACHE) || defined(USE_SDRAM) 
    RESERVE(___wab9=0x7FFFFFF - 75,___l9=76)  /* sdram */
#  endif
#endif /*} __WORKAROUND_AVOID_LDF_BLOCK_BOUNDARIES */

        l1_code
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
        } >MEM_L1_CODE

        l1_code_cache
        {
            INPUT_SECTION_ALIGN(4)
#if INSTR_CACHE /* { */
            ___l1_code_cache = 1;
#else
            ___l1_code_cache = 0;
            INPUT_SECTIONS( $OBJECTS(L1_code) $LIBRARIES(L1_code))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
#endif /* INSTR_CACHE } */
        } >MEM_L1_CODE_CACHE

        L1_data_a
        {
            INPUT_SECTION_ALIGN(4)
#if !DATAA_CACHE
            ___l1_data_cache_a = 0;
#endif
            INPUT_SECTIONS( $OBJECTS(L1_data_a) $LIBRARIES(L1_data_a))
            INPUT_SECTIONS( $OBJECTS(vtbl) $LIBRARIES(vtbl) )
            INPUT_SECTIONS( $OBJECTS(.frt) $LIBRARIES(.frt) )
            INPUT_SECTIONS( $OBJECTS(.frtl) $LIBRARIES(.frtl) )
            INPUT_SECTIONS( $OBJECTS(ctor) $LIBRARIES(ctor) )
            INPUT_SECTIONS( $OBJECTS(ctorl) $LIBRARIES(ctorl) )
            INPUT_SECTIONS( $OBJECTS(.gdt) $LIBRARIES(.gdt) )
            INPUT_SECTIONS( $OBJECTS(.gdtl) $LIBRARIES(.gdtl) )
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
        } >MEM_L1_DATA_A
 
        bsz_L1_data_a ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
        } >MEM_L1_DATA_A

#if DATAB_CACHE /* { */
        l1_data_b_cache
        {
            INPUT_SECTION_ALIGN(4)
            ___l1_data_cache_b = 1;
        } >MEM_L1_DATA_B_CACHE
#endif /* DATAB_CACHE } */

        L1_data_b
        {
            INPUT_SECTION_ALIGN(4)
#if !DATAB_CACHE
            ___l1_data_cache_b = 0;
#endif
            INPUT_SECTIONS( $OBJECTS(L1_data_b) $LIBRARIES(L1_data_b))
            INPUT_SECTIONS( $OBJECTS(bsz_init) $LIBRARIES(bsz_init))
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS( $OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS( $OBJECTS(constdata) $LIBRARIES(constdata))
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
        } >MEM_L1_DATA_B
        .meminit { ALIGN(4) } >MEM_L1_DATA_B

        bsz_L1_data_b ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
        } >MEM_L1_DATA_B

        stack
        {
            ldf_stack_space = .;
            ldf_stack_end = ldf_stack_space + MEMORY_SIZEOF(MEM_L1_DATA_B_STACK);
        } >MEM_L1_DATA_B_STACK

#if DATAA_CACHE /* { */
        l1_data_a_cache
        {
            INPUT_SECTION_ALIGN(4)
            ___l1_data_cache_a = 1;
        } >MEM_L1_DATA_A_CACHE
#if defined(PARTITION_EZKIT_SDRAM) /* { */
        heap
        {
            // Allocate a heap for the application
            ldf_heap_space = .;
            ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_BANK0) - 1;
            ldf_heap_length = ldf_heap_end - ldf_heap_space;        
        } >MEM_SDRAM0_BANK0
#else 
        heap
        {
            // Allocate a heap for the application
            ldf_heap_space = .;
            ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_SDRAM0_HEAP) - 1;
            ldf_heap_length = ldf_heap_end - ldf_heap_space;        
        } >MEM_SDRAM0_HEAP
#endif /* PARTITION_EZKIT_SDRAM } */
#else
        heap
        {
            // Allocate a heap for the application
            ldf_heap_space = .;
            ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(MEM_L1_DATA_A_CACHE) - 1;
            ldf_heap_length = ldf_heap_end - ldf_heap_space;        
        } >MEM_L1_DATA_A_CACHE
#endif /* DATAA_CACHE } */

#ifdef PARTITION_EZKIT_SDRAM /* { */
       sdram0_bank1
       {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(sdram0_bank1) $LIBRARIES(sdram0_bank1))
            INPUT_SECTIONS( $OBJECTS(sdram0_data) $LIBRARIES(sdram0_data))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
       } >MEM_SDRAM0_BANK1

       sdram0_bank1_bsz ZERO_INIT
       {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
       } >MEM_SDRAM0_BANK1

       sdram0_bank2
       {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(sdram0_bank2) $LIBRARIES(sdram0_bank2))
            INPUT_SECTIONS( $OBJECTS(sdram0_data) $LIBRARIES(sdram0_data))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
       } >MEM_SDRAM0_BANK2

       sdram0_bank2_bsz ZERO_INIT
       {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
       } >MEM_SDRAM0_BANK2

       sdram0_bank3
       {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(sdram0_bank3) $LIBRARIES(sdram0_bank3))
            INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
       } >MEM_SDRAM0_BANK3
#else /* PARTITION_EZKIT_SDRAM } { */
#if defined(USE_CACHE) || defined(USE_SDRAM) /* { */
        sdram
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(sdram0) $LIBRARIES(sdram0))
            INPUT_SECTIONS( $OBJECTS(noncache_code) $LIBRARIES(noncache_code))
            INPUT_SECTIONS( $OBJECTS(program) $LIBRARIES(program))
            INPUT_SECTIONS( $OBJECTS(cplb) $LIBRARIES(cplb))
            INPUT_SECTIONS( $OBJECTS(cplb_code) $LIBRARIES(cplb_code))
            INPUT_SECTIONS($OBJECTS(data1) $LIBRARIES(data1))
            INPUT_SECTIONS($OBJECTS(voldata) $LIBRARIES(voldata))
            INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))
            INPUT_SECTIONS( $OBJECTS(cplb_data) $LIBRARIES(cplb_data))
            INPUT_SECTIONS( $OBJECTS(.edt) $LIBRARIES(.edt) )
            INPUT_SECTIONS( $OBJECTS(.cht) $LIBRARIES(.cht) )
        } >MEM_SDRAM0

        bsz_sdram0 ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(bsz) $LIBRARIES(bsz))
        } >MEM_SDRAM0
#endif /* USE_CACHE || USE_SDRAM } */
#endif /* } */

  }
}
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