📄 var_misc.c
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/// fast access in the default interrupt vsr when umasking I0-I2 bits in
/// exr.
///
cyg_uint8 hal_int_prio_tbl[CYGNUM_HAL_ISR_COUNT] =
{
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
7, 7, 7, 7
};
//===========================================================================
// INTERRUPT ACKNOWLEDGE TABLE
// DESCRIPTION:
// This table contains all H8S/2674 interrupt status registers and the
// masks required for acknowledging the interrupt
//===========================================================================
///
/// This type stores mask and address of interrupt acknowledge register.
///
typedef struct
{
cyg_uint32 mask : 8; ///< interrupt acknowledge mask
cyg_uint32 address : 24; ///< interrupt acknowledge register
} int_ackn_t;
//
// Use this macro when entering entries into the hal_int_mask_tbl. We store the
// masks here so we do no need to do a not operation during runtime
//
#define ACKN_TBL_ENTRY(_int_status_reg_, _mask_) {(_mask_), (_int_status_reg_)}
#define CLR_BIT(_no_) ((cyg_uint8)(~(1 << (_no_))))
///
/// Interrupt acknowledge table.
/// This is the fix interrupt acknowledge table. It is const and so it will
/// reside within ROM.
///
const int_ackn_t hal_int_ackn_tbl[CYGNUM_HAL_ISR_COUNT] =
{
ACKN_TBL_ENTRY(0, 0), // 000 RSV
ACKN_TBL_ENTRY(0, 0), // 001 RSV
ACKN_TBL_ENTRY(0, 0), // 002 RSV
ACKN_TBL_ENTRY(0, 0), // 003 RSV
ACKN_TBL_ENTRY(0, 0), // 004 RSV
ACKN_TBL_ENTRY(0, 0), // 005 RSV
ACKN_TBL_ENTRY(0, 0), // 006 RSV
ACKN_TBL_ENTRY(0, 0), // 007 NMI
ACKN_TBL_ENTRY(0, 0), // 008 RSV
ACKN_TBL_ENTRY(0, 0), // 009 RSV
ACKN_TBL_ENTRY(0, 0), // 010 RSV
ACKN_TBL_ENTRY(0, 0), // 011 RSV
ACKN_TBL_ENTRY(0, 0), // 012 RSV
ACKN_TBL_ENTRY(0, 0), // 013 RSV
ACKN_TBL_ENTRY(0, 0), // 014 RSV
ACKN_TBL_ENTRY(0, 0), // 015 RSV
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(0)), // 016 IRQ 0
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(1)), // 017 IRQ 1
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(2)), // 018 IRQ 2
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(3)), // 019 IRQ 3
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(4)), // 020 IRQ 4
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(5)), // 021 IRQ 5
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(6)), // 022 IRQ 6
ACKN_TBL_ENTRY(CYGARC_ISRL, CLR_BIT(7)), // 023 IRQ 7
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(0)), // 024 IRQ 8
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(1)), // 025 IRQ 9
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(2)), // 026 IRQ 10
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(3)), // 027 IRQ 11
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(4)), // 028 IRQ 12
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(5)), // 029 IRQ 13
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(6)), // 030 IRQ 14
ACKN_TBL_ENTRY(CYGARC_ISRH, CLR_BIT(7)), // 031 IRQ 15
//---------------------------------------------------------------------------------
//
//
ACKN_TBL_ENTRY(0, 0), // 032 SWDTEND
ACKN_TBL_ENTRY(CYGARC_TCSRR, CLR_BIT(7)), // 033 WOVI
ACKN_TBL_ENTRY(0, 0), // 034 RSV
ACKN_TBL_ENTRY(CYGARC_REFCRH,CLR_BIT(7)), // 035 CMI
ACKN_TBL_ENTRY(0, 0), // 036 RSV
ACKN_TBL_ENTRY(0, 0), // 037 RSV
ACKN_TBL_ENTRY(CYGARC_ADCSR, CLR_BIT(7)), // 038 ADI
ACKN_TBL_ENTRY(0, 0), // 039 RSV
//---------------------------------------------------------------------------------
// TPU 0
//
ACKN_TBL_ENTRY(CYGARC_TSR0, CLR_BIT(0)), // 040 TGI0A
ACKN_TBL_ENTRY(CYGARC_TSR0, CLR_BIT(1)), // 041 TGI0B
ACKN_TBL_ENTRY(CYGARC_TSR0, CLR_BIT(2)), // 042 TGI0C
ACKN_TBL_ENTRY(CYGARC_TSR0, CLR_BIT(3)), // 043 TGI0D
ACKN_TBL_ENTRY(CYGARC_TSR0, CLR_BIT(4)), // 044 TCI0V
ACKN_TBL_ENTRY(0, 0), // 045 RSV
ACKN_TBL_ENTRY(0, 0), // 046 RSV
ACKN_TBL_ENTRY(0, 0), // 047 RSV
//---------------------------------------------------------------------------------
// TPU 1
//
ACKN_TBL_ENTRY(CYGARC_TSR1, CLR_BIT(0)), // 048 TGI1A
ACKN_TBL_ENTRY(CYGARC_TSR1, CLR_BIT(1)), // 049 TGI1B
ACKN_TBL_ENTRY(CYGARC_TSR1, CLR_BIT(4)), // 050 TCI1V
ACKN_TBL_ENTRY(CYGARC_TSR1, CLR_BIT(5)), // 051 TCI1U
//---------------------------------------------------------------------------------
// TPU 2
//
ACKN_TBL_ENTRY(CYGARC_TSR2, CLR_BIT(0)), // 052 TGI2A
ACKN_TBL_ENTRY(CYGARC_TSR2, CLR_BIT(1)), // 053 TGI2B
ACKN_TBL_ENTRY(CYGARC_TSR2, CLR_BIT(4)), // 054 TCI2V
ACKN_TBL_ENTRY(CYGARC_TSR2, CLR_BIT(5)), // 055 TCI2U
//---------------------------------------------------------------------------------
// TPU 3
//
ACKN_TBL_ENTRY(CYGARC_TSR3, CLR_BIT(0)), // 056 TGI3A
ACKN_TBL_ENTRY(CYGARC_TSR3, CLR_BIT(1)), // 057 TGI3B
ACKN_TBL_ENTRY(CYGARC_TSR3, CLR_BIT(2)), // 058 TGI3C
ACKN_TBL_ENTRY(CYGARC_TSR3, CLR_BIT(3)), // 059 TGI3D
ACKN_TBL_ENTRY(CYGARC_TSR3, CLR_BIT(4)), // 060 TCI3V
ACKN_TBL_ENTRY(0, 0), // 061 RSV
ACKN_TBL_ENTRY(0, 0), // 062 RSV
ACKN_TBL_ENTRY(0, 0), // 063 RSV
//---------------------------------------------------------------------------------
// TPU 4
//
ACKN_TBL_ENTRY(CYGARC_TSR4, CLR_BIT(0)), // 064 TGI4A
ACKN_TBL_ENTRY(CYGARC_TSR4, CLR_BIT(1)), // 065 TGI4B
ACKN_TBL_ENTRY(CYGARC_TSR4, CLR_BIT(4)), // 066 TCI4V
ACKN_TBL_ENTRY(CYGARC_TSR4, CLR_BIT(5)), // 067 TCI4U
//---------------------------------------------------------------------------------
// TPU 5
//
ACKN_TBL_ENTRY(CYGARC_TSR5, CLR_BIT(0)), // 068 TGI5A
ACKN_TBL_ENTRY(CYGARC_TSR5, CLR_BIT(1)), // 069 TGI5B
ACKN_TBL_ENTRY(CYGARC_TSR5, CLR_BIT(4)), // 070 TCI5V
ACKN_TBL_ENTRY(CYGARC_TSR5, CLR_BIT(5)), // 071 TCI5U
//---------------------------------------------------------------------------------
// TMR 0
//
ACKN_TBL_ENTRY(CYGARC_8TCSR0,CLR_BIT(6)), // 072 CMIA0
ACKN_TBL_ENTRY(CYGARC_8TCSR0,CLR_BIT(7)), // 073 CMIB0
ACKN_TBL_ENTRY(CYGARC_8TCSR0,CLR_BIT(5)), // 074 OVI0
ACKN_TBL_ENTRY(0, 0), // 075 RSV
//---------------------------------------------------------------------------------
// TMR 1
//
ACKN_TBL_ENTRY(CYGARC_8TCSR1,CLR_BIT(6)), // 076 CMIA1
ACKN_TBL_ENTRY(CYGARC_8TCSR1,CLR_BIT(7)), // 077 CMIB1
ACKN_TBL_ENTRY(CYGARC_8TCSR1,CLR_BIT(5)), // 078 OVI1
ACKN_TBL_ENTRY(0, 0), // 079 RSV
//---------------------------------------------------------------------------------
// DMAC
//
ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(4)), // 080 DMTEND0A
ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(5)), // 081 DMTEND0B
ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(6)), // 082 DMTEND1A
ACKN_TBL_ENTRY(CYGARC_DMABCRL, CLR_BIT(7)), // 083 DMTEND1B
//---------------------------------------------------------------------------------
// EXDMAC
//
ACKN_TBL_ENTRY(CYGARC_EDMDR0L, CLR_BIT(6)), // 084 EXDMTEND0A
ACKN_TBL_ENTRY(CYGARC_EDMDR1L, CLR_BIT(6)), // 085 EXDMTEND0B
ACKN_TBL_ENTRY(CYGARC_EDMDR2L, CLR_BIT(6)), // 086 EXDMTEND1A
ACKN_TBL_ENTRY(CYGARC_EDMDR3L, CLR_BIT(6)), // 087 EXDMTEND1B
//---------------------------------------------------------------------------------
// SCI 0
//
ACKN_TBL_ENTRY(CYGARC_SSR0, CLR_BIT(3) & CLR_BIT(4) & CLR_BIT(5)), // 088 ERI0
ACKN_TBL_ENTRY(CYGARC_SSR0, CLR_BIT(6)), // 089 RXI0
ACKN_TBL_ENTRY(CYGARC_SSR0, CLR_BIT(7)), // 090 TXI0
ACKN_TBL_ENTRY(CYGARC_SSR0, CLR_BIT(2)), // 091 TEI0
//---------------------------------------------------------------------------------
// SCI 1
//
ACKN_TBL_ENTRY(CYGARC_SSR1, CLR_BIT(3) & CLR_BIT(4) & CLR_BIT(5)), // 092 ERI1
ACKN_TBL_ENTRY(CYGARC_SSR1, CLR_BIT(6)), // 093 RXI1
ACKN_TBL_ENTRY(CYGARC_SSR1, CLR_BIT(7)), // 094 TXI1
ACKN_TBL_ENTRY(CYGARC_SSR1, CLR_BIT(2)), // 095 TEI1
//---------------------------------------------------------------------------------
// SCI 2
//
ACKN_TBL_ENTRY(CYGARC_SSR2, CLR_BIT(3) & CLR_BIT(4) & CLR_BIT(5)), // 096 ERI2
ACKN_TBL_ENTRY(CYGARC_SSR2, CLR_BIT(6)), // 097 RXI2
ACKN_TBL_ENTRY(CYGARC_SSR2, CLR_BIT(7)), // 098 TXI2
ACKN_TBL_ENTRY(CYGARC_SSR2, CLR_BIT(2)) // 099 TEI2
};
//===========================================================================
// INTERRUPT MASK TABLE
// DESCRIPTION:
// This table contains all H8S/2674 interrupt enable registers and the
// masks required for masking or unmasking an interrupt
//===========================================================================
///
/// This data type stores mask and address of one interrupt source
///
typedef struct
{
cyg_uint32 mask : 8; ///< interrupt mask to be applied
cyg_uint32 address : 24; ///< address of H8S interrupt anble register
} int_mask_t;
//
// Use this macro when entering entries into the hal_int_mask_tbl
//
#define MASK_TBL_ENTRY(_int_en_reg_, _mask_) {(_mask_), (_int_en_reg_)}
#define BIT(_no_) ((_no_))
//
// this define should be used for interrupt vectors without a mask
// register - i.e the NMI interrupt. This marks the interrupt as
// available because not available interrupts contain a 0
//
#define NO_MASK_REG 1
///
/// Interrupt mask table.
/// This is the fix interrupt mask table. It is const and so it will reside
/// within ROM.
///
const int_mask_t hal_int_mask_tbl[CYGNUM_HAL_ISR_COUNT] =
{
MASK_TBL_ENTRY(0, 0), // 000 RSV
MASK_TBL_ENTRY(0, 0), // 001 RSV
MASK_TBL_ENTRY(0, 0), // 002 RSV
MASK_TBL_ENTRY(0, 0), // 003 RSV
MASK_TBL_ENTRY(0, 0), // 004 RSV
MASK_TBL_ENTRY(0, 0), // 005 RSV
MASK_TBL_ENTRY(0, 0), // 006 RSV
MASK_TBL_ENTRY(NO_MASK_REG, 0), // 007 NMI
MASK_TBL_ENTRY(0, 0), // 008 RSV
MASK_TBL_ENTRY(0, 0), // 009 RSV
MASK_TBL_ENTRY(0, 0), // 010 RSV
MASK_TBL_ENTRY(0, 0), // 011 RSV
MASK_TBL_ENTRY(0, 0), // 012 RSV
MASK_TBL_ENTRY(0, 0), // 013 RSV
MASK_TBL_ENTRY(0, 0), // 014 RSV
MASK_TBL_ENTRY(0, 0), // 015 RSV
MASK_TBL_ENTRY(CYGARC_IERL, BIT(0)), // 016 IRQ 0
MASK_TBL_ENTRY(CYGARC_IERL, BIT(1)), // 017 IRQ 1
MASK_TBL_ENTRY(CYGARC_IERL, BIT(2)), // 018 IRQ 2
MASK_TBL_ENTRY(CYGARC_IERL, BIT(3)), // 019 IRQ 3
MASK_TBL_ENTRY(CYGARC_IERL, BIT(4)), // 020 IRQ 4
MASK_TBL_ENTRY(CYGARC_IERL, BIT(5)), // 021 IRQ 5
MASK_TBL_ENTRY(CYGARC_IERL, BIT(6)), // 022 IRQ 6
MASK_TBL_ENTRY(CYGARC_IERL, BIT(7)), // 023 IRQ 7
MASK_TBL_ENTRY(CYGARC_IERH, BIT(0)), // 024 IRQ 8
MASK_TBL_ENTRY(CYGARC_IERH, BIT(1)), // 025 IRQ 9
MASK_TBL_ENTRY(CYGARC_IERH, BIT(2)), // 026 IRQ 10
MASK_TBL_ENTRY(CYGARC_IERH, BIT(3)), // 027 IRQ 11
MASK_TBL_ENTRY(CYGARC_IERH, BIT(4)), // 028 IRQ 12
MASK_TBL_ENTRY(CYGARC_IERH, BIT(5)), // 029 IRQ 13
MASK_TBL_ENTRY(CYGARC_IERH, BIT(6)), // 030 IRQ 14
MASK_TBL_ENTRY(CYGARC_IERH, BIT(7)), // 031 IRQ 15
//---------------------------------------------------------------------------------
//
//
MASK_TBL_ENTRY(NO_MASK_REG, 0), // 032 SWDTEND
MASK_TBL_ENTRY(CYGARC_TCSRW, BIT(5)), // 033 WOVI
MASK_TBL_ENTRY(0, 0), // 034 RSV
MASK_TBL_ENTRY(CYGARC_REFCRH,BIT(6)), // 035 CMI
MASK_TBL_ENTRY(0, 0), // 036 RSV
MASK_TBL_ENTRY(0, 0), // 037 RSV
MASK_TBL_ENTRY(CYGARC_ADCSR, BIT(6)), // 038 ADI
MASK_TBL_ENTRY(0, 0), // 039 RSV
//---------------------------------------------------------------------------------
// TPU 0
//
MASK_TBL_ENTRY(CYGARC_TIER0, BIT(0)), // 040 TGI0A
MASK_TBL_ENTRY(CYGARC_TIER0, BIT(1)), // 041 TGI0B
MASK_TBL_ENTRY(CYGARC_TIER0, BIT(2)), // 042 TGI0C
MASK_TBL_ENTRY(CYGARC_TIER0, BIT(3)), // 043 TGI0D
MASK_TBL_ENTRY(CYGARC_TIER0, BIT(4)), // 044 TCI0V
MASK_TBL_ENTRY(0, 0), // 045 RSV
MASK_TBL_ENTRY(0, 0), // 046 RSV
MASK_TBL_ENTRY(0, 0), // 047 RSV
//---------------------------------------------------------------------------------
// TPU 1
//
MASK_TBL_ENTRY(CYGARC_TIER1, BIT(0)), // 048 TGI1A
MASK_TBL_ENTRY(CYGARC_TIER1, BIT(1)), // 049 TGI1B
MASK_TBL_ENTRY(CYGARC_TIER1, BIT(4)), // 050 TCI1V
MASK_TBL_ENTRY(CYGARC_TIER1, BIT(5)), // 051 TCI1U
//---------------------------------------------------------------------------------
// TPU 2
//
MASK_TBL_ENTRY(CYGARC_TIER2, BIT(0)), // 052 TGI2A
MASK_TBL_ENTRY(CYGARC_TIER2, BIT(1)), // 053 TGI2B
MASK_TBL_ENTRY(CYGARC_TIER2, BIT(4)), // 054 TCI2V
MASK_TBL_ENTRY(CYGARC_TIER2, BIT(5)), // 055 TCI2U
//---------------------------------------------------------------------------------
// TPU 3
//
MASK_TBL_ENTRY(CYGARC_TIER3, BIT(0)), // 056 TGI3A
MASK_TBL_ENTRY(CYGARC_TIER3, BIT(1)), // 057 TGI3B
MASK_TBL_ENTRY(CYGARC_TIER3, BIT(2)), // 058 TGI3C
MASK_TBL_ENTRY(CYGARC_TIER3, BIT(3)), // 059 TGI3D
MASK_TBL_ENTRY(CYGARC_TIER3, BIT(4)), // 060 TCI3V
MASK_TBL_ENTRY(0, 0), // 061 RSV
MASK_TBL_ENTRY(0, 0), // 062 RSV
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