var_misc.c

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

//==========================================================================
//
//      var_misc.c
//
//      HAL CPU variant miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    ysato
// Contributors: ysato, Uwe Kindler
// Date:         2003-12-06
// Purpose:      HAL miscellaneous functions
// Description:  This file contains miscellaneous functions provided by the
//               HAL.
//
//####DESCRIPTIONEND####
//
//==========================================================================


//==========================================================================
//                            DOXYGEN FILE HEADER
/// \file    var_misc.c
/// \brief   HAL miscellaneous functions.
/// \author  yoshinori sato, Uwe Kindler
/// \date    2003-12-06
///
/// This file contains miscellaneous functions provided by the HAL.
//==========================================================================


//==========================================================================
//                                 INCLUDES
//==========================================================================
#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>         // Base types
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros
#include <cyg/hal/var_arch.h>
#include <cyg/hal/var_intr.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_io.h>


//==========================================================================
//                          VARIANT INITIALIZATION
///
///  Complex initializations that cannot be done in assembly code.
//==========================================================================
void hal_variant_init(void)
{
    // Nothing to do here at the moment
}


//==========================================================================
//                     INTERRUPT REGISTER CONFIGURATION
// DESCRIPTION:
//     The following declarations and defines are required
//==========================================================================

//--------------------------------------------------------------------------
/// Interrupt configuration data structure.
/// This type contains the complete configuration data for one interrupt
/// source. The prio_reg_no is an index into hal_prio_reg_tbl[] and the
/// prio_bit_group tells us how often we have to shift the priority level
/// to get the value for priority register setting.
///
typedef struct {
    cyg_uint8 prio_reg_no    : 5; ///< priority register number
    cyg_uint8 prio_bit_group : 3; ///< priority bit group contains PRIO_XX_TO_YY
} int_prio_conf_t;


//--------------------------------------------------------------------------
// Priority bit group values for prio_bit_group member of hal_int_reg_conf
//
#define PRIO_RESERVED    7 // this is for reserved vectors - its just for doing an assertion
#define PRIO_14_TO_12    3
#define PRIO_10_TO_08    2
#define PRIO_06_TO_04    1
#define PRIO_02_TO_00    0

#define PRIO_BITGRP_MASK 3 // only 2 bits are valid here for priority bit group


//--------------------------------------------------------------------------
/// Interrupt priority register address table.
/// This table contains the addresses of all interrupt priority registers.
/// This table is indexed by the prio_reg_no in hal_int_reg_conf. The last
/// entry is for interrupt vectors which have no priotity. Last entry
/// points into ROM so nothing will be changed.
///
static const cyg_uint32 hal_prio_reg_tbl[] =
{
    CYGARC_IPRA,
    CYGARC_IPRB,
    CYGARC_IPRC,
    CYGARC_IPRD,
    CYGARC_IPRE,
    CYGARC_IPRF,
    CYGARC_IPRG,
    CYGARC_IPRH,
    CYGARC_IPRI,
    CYGARC_IPRJ,
    CYGARC_IPRK,
    0             ///< this entry marks an unused interrupt vector
};


//--------------------------------------------------------------------------
// These macros simplify entries into hal_int_prio_conf_tbl[]
//
#define PRIO_CONF_TBL_ENTRY(_prio_reg_no_, _bit_group_) {(_prio_reg_no_), (_bit_group_)}
#define IPR(_no_) ((_no_) - 'A')
#define IPR_NONE  11                // last entry in hal_prio_reg_tbl


//--------------------------------------------------------------------------
/// Interrupt priority configuration table.
/// This table stores priority registers and the bits to be set in these
/// registers to select a priority for a certain interrupt
///        
static const int_prio_conf_t hal_int_prio_conf_tbl[CYGNUM_HAL_ISR_COUNT] = 
{
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 000  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 001  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 002  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 003  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 004  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 005  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 006  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, 0),             // 007  NMI
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 008  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 009  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 010  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 011  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 012  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 013  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 014  RSV
    PRIO_CONF_TBL_ENTRY(IPR_NONE, PRIO_RESERVED), // 015  RSV
    PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_14_TO_12), // 016  IRQ 0
    PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_10_TO_08), // 017  IRQ 1
    PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_06_TO_04), // 018  IRQ 2
    PRIO_CONF_TBL_ENTRY(IPR('A'), PRIO_02_TO_00), // 019  IRQ 3
    PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_14_TO_12), // 020  IRQ 4
    PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_10_TO_08), // 021  IRQ 5
    PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_06_TO_04), // 022  IRQ 6
    PRIO_CONF_TBL_ENTRY(IPR('B'), PRIO_02_TO_00), // 023  IRQ 7
    PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_14_TO_12), // 024  IRQ 8
    PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_10_TO_08), // 025  IRQ 9
    PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_06_TO_04), // 026  IRQ 10
    PRIO_CONF_TBL_ENTRY(IPR('C'), PRIO_02_TO_00), // 027  IRQ 11
    PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_14_TO_12), // 028  IRQ 12
    PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_10_TO_08), // 029  IRQ 13
    PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_06_TO_04), // 030  IRQ 14
    PRIO_CONF_TBL_ENTRY(IPR('D'), PRIO_02_TO_00), // 031  IRQ 15

    //---------------------------------------------------------------------------------
    //
    //
    PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_14_TO_12), // 032  SWDTEND
    PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_10_TO_08), // 033  WOVI
    PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_06_TO_04), // 034  RSV
    PRIO_CONF_TBL_ENTRY(IPR('E'), PRIO_02_TO_00), // 035  CMI
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_RESERVED), // 036  RSV
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_RESERVED), // 037  RSV
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_10_TO_08), // 038  ADI
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_10_TO_08), // 039  RSV
    
    //---------------------------------------------------------------------------------
    // TPU 0
    //
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 040  TGI0A
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 041  TGI0B
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 042  TGI0C
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 043  TGI0D
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_06_TO_04), // 044  TCI0V
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_RESERVED), // 045  RSV
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_RESERVED), // 046  RSV
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_RESERVED), // 047  RSV

    //---------------------------------------------------------------------------------
    // TPU 1
    //
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 048  TGI1A
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 049  TGI1B
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 050  TCI1V
    PRIO_CONF_TBL_ENTRY(IPR('F'), PRIO_02_TO_00), // 051  TCI1U
    
    //---------------------------------------------------------------------------------
    // TPU 2
    //
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 052  TGI2A
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 053  TGI2B
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 054  TCI2V
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_14_TO_12), // 055  TCI2U
    
    //---------------------------------------------------------------------------------
    // TPU 3
    //
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 056  TGI3A
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 057  TGI3B
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 058  TGI3C
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 059  TGI3D
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_10_TO_08), // 060  TCI3V
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_RESERVED), // 061  RSV
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_RESERVED), // 062  RSV
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_RESERVED), // 063  RSV
    
    //---------------------------------------------------------------------------------
    // TPU 4
    //
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 064  TGI4A 
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 065  TGI4B
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 066  TCI4V
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_06_TO_04), // 067  TCI4U

    //---------------------------------------------------------------------------------
    // TPU 5
    //
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 068  TGI5A
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 069  TGI5B
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 070  TCI5V
    PRIO_CONF_TBL_ENTRY(IPR('G'), PRIO_02_TO_00), // 071  TCI5U
    
    //---------------------------------------------------------------------------------
    // TMR 0
    //
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 072  CMIA0
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 073  CMIB0
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_14_TO_12), // 074  OVI0
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_RESERVED), // 075  RSV
    
    //---------------------------------------------------------------------------------
    // TMR 1
    //
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 076  CMIA1
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 077  CMIB1
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_10_TO_08), // 078  OVI1
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_RESERVED), // 079  RSV
    
    //---------------------------------------------------------------------------------
    // DMAC
    //
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 080  DMTEND0A
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 081  DMTEND0B
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 082  DMTEND1A
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_06_TO_04), // 083  DMTEND1B
    
    //---------------------------------------------------------------------------------
    // EXDMAC
    //
    PRIO_CONF_TBL_ENTRY(IPR('H'), PRIO_02_TO_00), // 084  EXDMTEND0A
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_14_TO_12), // 085  EXDMTEND0B
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_10_TO_08), // 086  EXDMTEND1A
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_06_TO_04), // 087  EXDMTEND1B

    //---------------------------------------------------------------------------------
    // SCI 0
    //
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 088  ERI0
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 089  RXI0
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 090  TXI0
    PRIO_CONF_TBL_ENTRY(IPR('I'), PRIO_02_TO_00), // 091  TEI0

    //---------------------------------------------------------------------------------
    // SCI 1
    //
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 092  ERI1
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 093  RXI1
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 094  TXI1
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_14_TO_12), // 095  TEI1

    //---------------------------------------------------------------------------------
    // SCI 2
    //
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 096  ERI2
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 097  RXI2
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 098  TXI2
    PRIO_CONF_TBL_ENTRY(IPR('J'), PRIO_10_TO_08), // 099  TEI2
}; 

//--------------------------------------------------------------------------
/// Interrupt priority table.
/// This table stores the priority settings for all interrupt sources for