mod_regs_tmr.h

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

#ifndef CYGONCE_MOD_REGS_TMR_H
#define CYGONCE_MOD_REGS_TMR_H

//==========================================================================
//
//      mod_regs_tmr.h
//
//       TPU/TMR Register
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    yoshinori sato
// Contributors: yoshinori sato, Uwe Kindler
// Date:         2003-12-06
//              
//####DESCRIPTIONEND####
//
//==========================================================================


//==========================================================================
//                            DOXYGEN FILE HEADER
/// \file    mod_regs_tmr.h
/// \brief   TPU/TMR Register definitions.
/// \author  yoshinori sato, Uwe Kindler
/// \date    2003-12-06
//==========================================================================


//==========================================================================
//                            16-Bit Timer Unit (TPU)
//==========================================================================
#define CYGARC_TSTR   0xFFFFC0
#define CYGARC_TSNC   0XFFFFC1

//--------------------------------------------------------------------------
// Timer 0
//
#define CYGARC_TCR0   0xFFFFD0
#define CYGARC_TMDR0  0xFFFFD1
#define CYGARC_TIORH0 0xFFFFD2
#define CYGARC_TIORL0 0xFFFFD3
#define CYGARC_TIER0  0xFFFFD4
#define CYGARC_TSR0   0xFFFFD5
#define CYGARC_TCNT0  0xFFFFD6
#define CYGARC_TGRA0  0xFFFFD8
#define CYGARC_TGRB0  0xFFFFDA
#define CYGARC_TGRC0  0xFFFFDC
#define CYGARC_TGRD0  0xFFFFDE

//--------------------------------------------------------------------------
// Timer 1
//
#define CYGARC_TCR1   0xFFFFE0
#define CYGARC_TMDR1  0xFFFFE1
#define CYGARC_TIOR1  0xFFFFE2
#define CYGARC_TIER1  0xFFFFE4
#define CYGARC_TSR1   0xFFFFE5
#define CYGARC_TCNT1  0xFFFFE6
#define CYGARC_TGRA1  0xFFFFE8
#define CYGARC_TGRB1  0xFFFFEA

//--------------------------------------------------------------------------
// Timer 2
//
#define CYGARC_TCR2   0xFFFFF0
#define CYGARC_TMDR2  0xFFFFF1
#define CYGARC_TIOR2  0xFFFFF2
#define CYGARC_TIER2  0xFFFFF4
#define CYGARC_TSR2   0xFFFFF5
#define CYGARC_TCNT2  0xFFFFF6
#define CYGARC_TGRA2  0xFFFFF8
#define CYGARC_TGRB2  0xFFFFFA

//--------------------------------------------------------------------------
// Timer 3
//
#define CYGARC_TCR3   0xFFFE80
#define CYGARC_TMDR3  0xFFFE81
#define CYGARC_TIORH3 0xFFFE82
#define CYGARC_TIORL3 0xFFFE83
#define CYGARC_TIER3  0xFFFE84
#define CYGARC_TSR3   0xFFFE85
#define CYGARC_TCNT3  0xFFFE86
#define CYGARC_TGRA3  0xFFFE88
#define CYGARC_TGRB3  0xFFFE8A
#define CYGARC_TGRC3  0xFFFE8C
#define CYGARC_TGRD3  0xFFFE8E

//--------------------------------------------------------------------------
// Timer 4
//
#define CYGARC_TCR4   0xFFFE90
#define CYGARC_TMDR4  0xFFFE91
#define CYGARC_TIOR4  0xFFFE92
#define CYGARC_TIER4  0xFFFE94
#define CYGARC_TSR4   0xFFFE95
#define CYGARC_TCNT4  0xFFFE96
#define CYGARC_TGRA4  0xFFFE98
#define CYGARC_TGRB4  0xFFFE9A

//--------------------------------------------------------------------------
// Timer 5
//
#define CYGARC_TCR5   0xFFFEA0
#define CYGARC_TMDR5  0xFFFEA1
#define CYGARC_TIOR5  0xFFFEA2
#define CYGARC_TIER5  0xFFFEA4
#define CYGARC_TSR5   0xFFFEA5
#define CYGARC_TCNT5  0xFFFEA6
#define CYGARC_TGRA5  0xFFFEA8
#define CYGARC_TGRB5  0xFFFEAA

//--------------------------------------------------------------------------
// Register Bit definition for TPU
//
// TCR bit definitions
//
#define CYGARC_TCR_CLR_CMA     0x20  // TCNT cleared by TGRA compare match/input capture
#define CYGARC_TCR_CLR_CMB     0x40  // TCNT cleared by TGRB compare match/input capture
#define CYGARC_TCR_CLR_CMC     0xA0  // TCNT cleared by TGRC compare match/input capture
#define CYCARC_TCR_CLR_CMD     0xC0  // TCNT cleared by TGRA compare match/input capture
#define CYGARC_TCR_CKE_RISING  0x00  // Count at rising input cock edge
#define CYGARC_TCR_CKE_FALLING 0x08  // Count at falling input cock edge
#define CYGARC_TCR_CKE_BOTH    0x10  // Count at both input cock edges
#define CYGARC_TCR_TPSC_1      0x00  // Internal clock: counts on clock/1
#define CYGARC_TCR_TPSC_4      0x01  // Internal clock: counts on clock/4
#define CYGARC_TCR_TPSC_16     0x02  // Internal clock: counts on clock/16
#define CYGARC_TCR_TPSC_64     0x03  // Internal clock: counts on clock/64
//
// TSTR - Counter start 0 - 5
//
#define CYGARC_TSTR_CST0       0x01  
#define CYGARC_TSTR_CST1       0x02
#define CYGARC_TSTR_CST2       0x04
#define CYGARC_TSTR_CST3       0x08
#define CYGARC_TSTR_CST4       0x10
#define CYGARC_TSTR_CST5       0x20
//
// TSR bit definitions
//
#define CYGARC_TSR_TCFD        0x80
#define CYGARC_TSR_RSV6        0x40
#define CYGARC_TSR_TCFU        0x20
#define CYGARC_TSR_TCFV        0x10
#define CYGARC_TSR_TGFD        0x08
#define CYGARC_TSR_TGFC        0x04
#define CYGARC_TSR_TGFB        0x02
#define CYGARC_TSR_TGFA        0x01


//==========================================================================
//                            8-Bit Timers (TMR)
//==========================================================================

//--------------------------------------------------------------------------
// TCR selects the clock source and the time at which TCNT is cleared, and 
// controls interrupts.
//
// Register Addresses:
//
#define CYGARC_8TCR0   0xFFFFB0
#define CYGARC_8TCR1   0xFFFFB1
//
// TCR Bit definitions
// 
#define CYGARC_8TCR_CMIEB     0x80       // Compare Match Interrupt Enable B
#define CYGARC_8TCR_CMIEA     0x40       // Compare Match Interrupt Enable A
#define CYGARC_8TCR_OVIE      0x20       // Timer Overflow Interrupt Enable
#define CYGARC_8TCR_CLR_DIS   0x00       // TCNT clearing disabled
#define CYGARC_8TCR_CLR_CMA   0x08       // TCNT clear by compare match A
#define CYGARC_8TCR_CLR_CMB   0x10       // TCNT clear by compare match B
#define CYGARC_8TCR_CLR_EXT   0x18       // TCNT clear by rising edge of external reset input
#define CYGARC_8TCR_CKS_DIS   0x00       // Clock input disabled
#define CYGARC_8TCR_CKS_8     0x01       // Internal clock, counted at falling edge of clock/8
#define CYGARC_8TCR_CKS_64    0x02       // Internal clock, counted at falling edge of clock/8
#define CYGARC_8TCR_CKS_8192  0x03       // Internal clock, counted at falling edge of clock/8
#define CYGARC_8TCR_CKS_TCNT  0x04       // Count at TCNT_x overflow signal


//--------------------------------------------------------------------------
// TCSR displays status flags, and controls compare match output.
//
// Register Addresses:
//
#define CYGARC_8TCSR0  0xFFFFB2
#define CYGARC_8TCSR1  0xFFFFB3
//
// TCSR bit definitions
//
#define CYGARC_8TSCR_CMFB         0x80  // compare match flag B
#define CYGARC_8TSCR_CMFA         0x40  // compare match flag A
#define CYGARC_8TSCR_OVF          0x20  // timer overflow flag
#define CYGARC_8TSCR_ADTE         0x10  // A/D Trigger enable
#define CYGARC_8TSCR_CMB_OUT_NO   0x00  // 00: No change when compare match B occurs
#define CYGARC_8TSCR_CMB_OUT_0    0x04  // 01: 0 is output when compare match B occurs
#define CYGARC_8TSCR_CMB_OUT_1    0x08  // 10: 1 is output when compare match B occurs
#define CYGARC_8TSCR_CMB_OUT_TOG  0x0C  // 11: Output is inverted when compare match B occurs (toggle output)
#define CYGARC_8TSCR_CMA_OUT_NO   0x00  // 00: No change when compare match A occurs
#define CYGARC_8TSCR_CMA_OUT_0    0x01  // 01: 0 is output when compare match A occurs
#define CYGARC_8TSCR_CMA_OUT_1    0x02  // 10: 1 is output when compare match A occurs
#define CYGARC_8TSCR_CMA_OUT_TOG  0x03  // 11: Output is inverted when compare match A occurs (toggle output)


#define CYGARC_8TCORA0 0xFFFFB4
#define CYGARC_8TCORA1 0xFFFFB5
#define CYGARC_8TCORB0 0xFFFFB6
#define CYGARC_8TCORB1 0xFFFFB7
#define CYGARC_8TCNT0  0xFFFFB8
#define CYGARC_8TCNT1  0xFFFFB9


//---------------------------------------------------------------------------
#endif // End of #define CYGONCE_MOD_REGS_TMR_H