var_intr_numbers.h

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

#ifndef CYGONCE_HAL_VAR_INTR_NUMBERS_H
#define CYGONCE_HAL_VAR_INTR_NUMBERS_H
//==========================================================================
//
//      var_intr.h
//
//      H8S Interrupt vectors definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// the terms of the GNU General Public License as published by the Free
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//
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
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// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Uwe Kindler
// Contributors: Uwe Kindler
// Date:         2003-12-06
// Purpose:      H8S Interrupt Support
// Description:  These are H8S/2674 interrupt vector definitions.
//              
// Usage:
//              #include <cyg/hal/var_intr.h>
//              ...
//              
//
//####DESCRIPTIONEND####
//
//==========================================================================


//==========================================================================
//                            DOXYGEN FILE HEADER
/// \file    var_intr_numbers.h
/// \brief   These are H8S/2674 interrupt vector definitions.
/// \author  Uwe Kindler
/// \date    2003-12-06
//==========================================================================


//==========================================================================
//                                  H8S VECTORS
// DESCRIPTION:
//     Standard exception vectors supported by H8S. We have 128 
//     exception vectors in H8S architecture. 
//==========================================================================
#define CYGNUM_HAL_VECTOR_RESET_POWER_ON       0  
#define CYGNUM_HAL_VECTOR_RESET_MANUAL         1
#define CYGNUM_HAL_VECTOR_RSV2                 2
#define CYGNUM_HAL_VECTOR_RSV3                 3
#define CYGNUM_HAL_VECTOR_RSV4                 4
#define CYGNUM_HAL_VECTOR_TRACE                5
#define CYGNUM_HAL_VECTOR_DIRECT_TRANS         6  
#define CYGNUM_HAL_VECTOR_NMI                  7   // interrupt
#define CYGNUM_HAL_VECTOR_TRAP0                8
#define CYGNUM_HAL_VECTOR_TRAP1                9
#define CYGNUM_HAL_VECTOR_TRAP2                10
#define CYGNUM_HAL_VECTOR_TRAP3                11


//==========================================================================
//                                 H8S EXCEPTIONS
// DESCRIPTION:
//     Exception numbers of synchronous exceptions. These are the values 
//     used when passed out to an external exception handler using 
//     cyg_hal_deliver_exception().
//==========================================================================
#define CYGNUM_HAL_EXCEPTION_TRACE             CYGNUM_HAL_VECTOR_TRACE
#define CYGNUM_HAL_EXCEPTION_DIRECT_TRANS      CYGNUM_HAL_VECTOR_DIRECT_TRANS
#define CYGNUM_HAL_EXCEPTION_TRAP0             CYGNUM_HAL_VECTOR_TRAP0
#define CYGNUM_HAL_EXCEPTION_TRAP1             CYGNUM_HAL_VECTOR_TRAP1
#define CYGNUM_HAL_EXCEPTION_TRAP2             CYGNUM_HAL_VECTOR_TRAP2
#define CYGNUM_HAL_EXCEPTION_TRAP3             CYGNUM_HAL_VECTOR_TRAP3


#define CYGNUM_HAL_EXCEPTION_MIN               CYGNUM_HAL_VECTOR_TRACE
#define CYGNUM_HAL_EXCEPTION_MAX               CYGNUM_HAL_VECTOR_TRAP3
#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN +1)


//==========================================================================
//                              H8S INTERRUPT VECTORS
// DESCRIPTION:
//     These are the definition for the H8S2674 interrupt vectors and
//     numbers for range checking. 
//
// NOTES:
//     Because interrupts and exceptions are mixed within the 128 H8S 
//     exception vectors we have to define 128 ISR. Normally interrupts
//     start at vector number 16 but vector number 6, and 7 (NMI) are also
//     external interrupts. In order to avoid adress translations we define
//     the ISR table starting at vector 0. 
//==========================================================================

//--------------------------------------------------------------------------
// external interrupts within the exception vectors
//
#define CYGNUM_HAL_INTERRUPT_NMI                7

//--------------------------------------------------------------------------
// external interrupts
//
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0        16
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1        17
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2        18
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3        19
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4        20
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5        21
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6        22
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7        23
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_8        24
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_9        25
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_10       26
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_11       27
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_12       28
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_13       29
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_14       30
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_15       31

//--------------------------------------------------------------------------
//
//
#define CYGNUM_HAL_INTERRUPT_SWDTEND           32
#define CYGNUM_HAL_INTERRUPT_WOVI              33
#define CYGNUM_HAL_INTERRUPT_RSV34             34
#define CYGNUM_HAL_INTERRUPT_RFSH_CMI          35
#define CYGNUM_HAL_INTERRUPT_RSV36             36
#define CYGNUM_HAL_INTERRUPT_RSV37             37
#define CYGNUM_HAL_INTERRUPT_ADI               38
#define CYGNUM_HAL_INTERRUPT_RSV39             39

//--------------------------------------------------------------------------
// TPU 0
//
#define CYGNUM_HAL_INTERRUPT_TGI0A             40
#define CYGNUM_HAL_INTERRUPT_TGI0B             41
#define CYGNUM_HAL_INTERRUPT_TGI0C             42
#define CYGNUM_HAL_INTERRUPT_TGI0D             43
#define CYGNUM_HAL_INTERRUPT_TCI0V             44
#define CYGNUM_HAL_INTERRUPT_RSV45             45
#define CYGNUM_HAL_INTERRUPT_RSV46             46
#define CYGNUM_HAL_INTERRUPT_RSV47             47

//--------------------------------------------------------------------------
// TPU 1
//
#define CYGNUM_HAL_INTERRUPT_TGI1A             48
#define CYGNUM_HAL_INTERRUPT_TGI1B             49
#define CYGNUM_HAL_INTERRUPT_TCI1V             50
#define CYGNUM_HAL_INTERRUPT_TCI1U             51

//--------------------------------------------------------------------------
// TPU 2
//
#define CYGNUM_HAL_INTERRUPT_TGI2A             52
#define CYGNUM_HAL_INTERRUPT_TGI2B             53
#define CYGNUM_HAL_INTERRUPT_TCI2V             54
#define CYGNUM_HAL_INTERRUPT_TCI2U             55

//--------------------------------------------------------------------------
// TPU 3
//
#define CYGNUM_HAL_INTERRUPT_TGI3A             56
#define CYGNUM_HAL_INTERRUPT_TGI3B             57
#define CYGNUM_HAL_INTERRUPT_TGI3C             58
#define CYGNUM_HAL_INTERRUPT_TGI3D             59
#define CYGNUM_HAL_INTERRUPT_TCI3V             60
#define CYGNUM_HAL_INTERRUPT_RSV61             61
#define CYGNUM_HAL_INTERRUPT_RSV62             62
#define CYGNUM_HAL_INTERRUPT_RSV63             63

//--------------------------------------------------------------------------
// TPU 4
//
#define CYGNUM_HAL_INTERRUPT_TGI4A             64
#define CYGNUM_HAL_INTERRUPT_TGI4B             65
#define CYGNUM_HAL_INTERRUPT_TCI4V             66
#define CYGNUM_HAL_INTERRUPT_TCI4U             67

//--------------------------------------------------------------------------
// TPU 5
//
#define CYGNUM_HAL_INTERRUPT_TGI5A             68
#define CYGNUM_HAL_INTERRUPT_TGI5B             69
#define CYGNUM_HAL_INTERRUPT_TCI5V             70
#define CYGNUM_HAL_INTERRUPT_TCI5U             71

//--------------------------------------------------------------------------
// TMR 0
//
#define CYGNUM_HAL_INTERRUPT_CMIA0             72
#define CYGNUM_HAL_INTERRUPT_CMIB0             73
#define CYGNUM_HAL_INTERRUPT_OVI0              74
#define CYGNUM_HAL_INTERRUPT_RSV75             75

//--------------------------------------------------------------------------
// TMR 1
//
#define CYGNUM_HAL_INTERRUPT_CMIA1             76
#define CYGNUM_HAL_INTERRUPT_CMIB1             77
#define CYGNUM_HAL_INTERRUPT_OVI1              78
#define CYGNUM_HAL_INTERRUPT_RSV79             79

//--------------------------------------------------------------------------
// DMAC
//
#define CYGNUM_HAL_INTERRUPT_DEND0A            80
#define CYGNUM_HAL_INTERRUPT_DEND0B            81
#define CYGNUM_HAL_INTERRUPT_DEND1A            82
#define CYGNUM_HAL_INTERRUPT_DEND1B            83

//--------------------------------------------------------------------------
// EXDMAC
//
#define CYGNUM_HAL_INTERRUPT_EXDEND0           84
#define CYGNUM_HAL_INTERRUPT_EXDEND1           85
#define CYGNUM_HAL_INTERRUPT_EXDEND2           86
#define CYGNUM_HAL_INTERRUPT_EXDEND3           87

//--------------------------------------------------------------------------
// SCI 0
//
#define CYGNUM_HAL_INTERRUPT_ERI0              88
#define CYGNUM_HAL_INTERRUPT_RXI0              89
#define CYGNUM_HAL_INTERRUPT_TXI0              90
#define CYGNUM_HAL_INTERRUPT_TEI0              91

//--------------------------------------------------------------------------
// SCI 1
//
#define CYGNUM_HAL_INTERRUPT_ERI1              92
#define CYGNUM_HAL_INTERRUPT_RXI1              93
#define CYGNUM_HAL_INTERRUPT_TXI1              94
#define CYGNUM_HAL_INTERRUPT_TEI1              95

//--------------------------------------------------------------------------
// SCI 2
//
#define CYGNUM_HAL_INTERRUPT_ERI2              96
#define CYGNUM_HAL_INTERRUPT_RXI2              97
#define CYGNUM_HAL_INTERRUPT_TXI2              98
#define CYGNUM_HAL_INTERRUPT_TEI2              99
//
// The following vectors 100 - 127 are reserved an do not generate any
// interrupt. Therefore we do not use them and do not reserve memory
// within interrupt tables
//


//--------------------------------------------------------------------------
// some definitions for range checking
// The interrupt table is defined for vector 0 - 99 but the first valid
// vector is vector 7 CYGNUM_HAL_INTERRUPT_NMI
//
#define CYGNUM_HAL_ISR_MIN                     CYGNUM_HAL_INTERRUPT_NMI
#define CYGNUM_HAL_ISR_MAX                     CYGNUM_HAL_INTERRUPT_TEI2
#define CYGNUM_HAL_ISR_COUNT                   CYGNUM_HAL_ISR_MAX + 1
#define CYGNUM_HAL_ISR_FIRST_EXT               CYGNUM_HAL_INTERRUPT_EXTERNAL_0
#define CYGNUM_HAL_ISR_LAST_INT                CYGNUM_HAL_INTERRUPT_TEI2 
         
 
//==========================================================================
//                            REALTIME CLOCK VECTOR
// DESCRIPTION:
//     The vector used by the real time clock 
//==========================================================================
#define CYGNUM_HAL_INTERRUPT_RTC                CYGNUM_HAL_INTERRUPT_TGI5A

//--------------------------------------------------------------------------
#endif // #ifndef CYGONCE_HAL_VAR_INTR_NUMBERS_H
// End of var_intr_numbers.h