intnest.c

ecos移植到R8H系列的源码。源码包来自http://www.cetoni.de/develop/develop_ecosh8s_en.html

//=================================================================
//
//        intnest.c
//
//        Test of interrupt nesting
//
//=================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):     Uwe Kindler
// Contributors:  Uwe Kindler
// Date:          2004-02-14
// Description:   Checks interrupt nesting. H8S architecture supports 8 
//                different interrupt levels. When nesting is enabled then
//                an ISR can be interrupted by a higher priority interrupt.
//                A maximum nesting of 7 interrupts may occur:
//                priority 1 - priotity 7. This test checks if the maximum
//                nesting will be reached without any problems. It starts
//                7 different hardware timers with 7 different interrupt
//                priorities.
//####DESCRIPTIONEND####
//===========================================================================


//===========================================================================
//                                  INCLUDES
//===========================================================================
#include <pkgconf/hal.h>
#include <cyg/infra/diag.h>
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_arch.h>           /* CYGNUM_HAL_STACK_SIZE_TYPICAL */
#include <cyg/infra/testcase.h>
#include <cyg/kernel/kapi.h>            /* All the kernel specific stuff */
#include <cyg/hal/hal_if.h>

//
// check if kernel API C is present - it's required for this test
//
#ifdef CYGFUN_KERNEL_API_C
#include <cyg/hal/hal_intr.h>
#include "testaux.h"


//===========================================================================
//                                  DEFINES
//===========================================================================
#define ONE_SHOT        0
#define SECONDS(_s_)    ((_s_) * 100)


//===========================================================================
//                                  TYPES
//===========================================================================
typedef struct _int_test_conf
{
    cyg_interrupt obj;
    cyg_handle_t  hdl;
    cyg_uint8     prio;
} int_test_conf_t;


//===========================================================================
//                                LOCALS
// DESCRIPTTION:
//     Now declare (and allocate space for) some kernel stuf
//===========================================================================
//
// thread stuff
//
cyg_thread         thread_tmr_obj;            // space for thread object
cyg_uint32         thread_tmr_stack[1024];    // stacks 4096 byte
cyg_handle_t       thread_tmr_hdl;  
cyg_thread_entry_t thread_tmr_entry;          // and now variables for the procedure which is the thread

//
// interrupt stuff
//
int_test_conf_t    int_tpu0;
int_test_conf_t    int_tpu1;
int_test_conf_t    int_tpu2;
int_test_conf_t    int_tpu3;
int_test_conf_t    int_tpu4;
int_test_conf_t    int_tmr0;
int_test_conf_t    int_tmr1;

cyg_uint8          nesting_ctr = 0;


//===========================================================================
//                              LOCAL FUNCTIONS
//===========================================================================
void tpu0_setup(void);
void tpu1_setup(void);
void tpu2_setup(void);
void tpu3_setup(void);
void tpu4_setup(void);
void tmr0_setup(void);
void tmr1_setup(void);


//===========================================================================
//                                  TPU0 ISR
//===========================================================================
cyg_uint32 tpu0_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    
    nesting_ctr++; 
    diag_printf("ISR: TPU0   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);   
    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TCI1V);
    //
    // now wait 4 second - this should be enougth time for all other ISRs to
    // run. If the ISR reaches the code behind the delay the test failed because
    // when the other ISRs run this ISR will be blocked
    //
    CYGACC_CALL_IF_DELAY_US(4000000);	
    //
    // if nesting is enabled then we should never reach the following statement
    // and the test fails if we do. If interrupt nesting is disabled then we have to
    // reach the following statement.
    //
#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING
    CYG_TEST_FAIL_FINISH("Interrupt nesting not possible");
#else
    CYG_TEST_PASS_FINISH("Interrupt nesting disabled and not occured - OK");
#endif
    while (1)
    {
    }
}


//===========================================================================
//                                  TPU1 ISR
//===========================================================================
cyg_uint32 tpu1_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    nesting_ctr++;
    diag_printf("ISR: TPU1   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);
    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TCI2V);
    //
    // now wait 4 second - this should be enougth time for all other ISRs to
    // run. If the ISR reaches the code behind the delay the test failed because
    // when the other ISRs run this ISR will be blocked
    //
    CYGACC_CALL_IF_DELAY_US(4000000);	
    
    CYG_TEST_FAIL_FINISH("Interrupt nesting not possible");
    while (1)
    {
    }
}


//===========================================================================
//                                  TPU2 ISR
//===========================================================================
cyg_uint32 tpu2_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    nesting_ctr++;
    diag_printf("ISR: TPU2   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);
    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TCI3V);
    //
    // now wait 4 second - this should be enougth time for all other ISRs to
    // run. If the ISR reaches the code behind the delay the test failed because
    // when the other ISRs run this ISR will be blocked
    //
    CYGACC_CALL_IF_DELAY_US(4000000);	
    
    CYG_TEST_FAIL_FINISH("Interrupt nesting not possible");
    while (1)
    {
    }
}


//===========================================================================
//                                  TPU3 ISR
//===========================================================================
cyg_uint32 tpu3_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    nesting_ctr++;
    diag_printf("ISR: TPU3   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);
    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_TCI4V);
    //
    // now wait 4 second - this should be enougth time for all other ISRs to
    // run. If the ISR reaches the code behind the delay the test failed because
    // when the other ISRs run this ISR will be blocked
    //
    CYGACC_CALL_IF_DELAY_US(4000000);	
    
    CYG_TEST_FAIL_FINISH("Interrupt nesting not possible");
    while (1)
    {
    }
}


//===========================================================================
//                                  TPU4 ISR
//===========================================================================
cyg_uint32 tpu4_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    nesting_ctr++;
    diag_printf("ISR: TPU4   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);
    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_OVI0);
    //
    // now wait 4 second - this should be enougth time for all other ISRs to
    // run. If the ISR reaches the code behind the delay the test failed because
    // when the other ISRs run this ISR will be blocked
    //
    CYGACC_CALL_IF_DELAY_US(4000000);	
    
    CYG_TEST_FAIL_FINISH("Interrupt nesting not possible");
    while (1)
    {
    }
}


//===========================================================================
//                                  TMR0 ISR
//===========================================================================
cyg_uint32 tmr0_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    nesting_ctr++;
    diag_printf("ISR: TMR0   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);
    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_OVI1);
    //
    // now wait 4 second - this should be enougth time for all other ISRs to
    // run. If the ISR reaches the code behind the delay the test failed because
    // when the other ISRs run this ISR will be blocked
    //
    CYGACC_CALL_IF_DELAY_US(4000000);	
    
    CYG_TEST_FAIL_FINISH("Interrupt nesting not possible");
    while (1)
    {
    }
}


//===========================================================================
//                                  TMR1 ISR
//===========================================================================
cyg_uint32 tmr1_ISR(cyg_vector_t vector, cyg_addrword_t pdata)
{
    cyg_uint8 level = *(cyg_uint8 *)pdata;
    
    nesting_ctr++;
    diag_printf("ISR: TMR1   PRIORITY LEVEL: %d    NESTING: %d\n", level, nesting_ctr);
    
    CYG_TEST_PASS_FINISH("Interrupt nesting OK");

    return CYG_ISR_HANDLED;
}


//===========================================================================
//                                  NMI THREAD
//===========================================================================